part4.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "segment7:unit3\|display\[0\] " "Warning: Node \"segment7:unit3\|display\[0\]\" is a latch" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segment7:unit3\|display\[1\] " "Warning: Node \"segment7:unit3\|display\[1\]\" is a latch" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segment7:unit3\|display\[2\] " "Warning: Node \"segment7:unit3\|display\[2\]\" is a latch" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segment7:unit3\|display\[3\] " "Warning: Node \"segment7:unit3\|display\[3\]\" is a latch" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segment7:unit3\|display\[4\] " "Warning: Node \"segment7:unit3\|display\[4\]\" is a latch" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segment7:unit3\|display\[5\] " "Warning: Node \"segment7:unit3\|display\[5\]\" is a latch" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segment7:unit3\|display\[6\] " "Warning: Node \"segment7:unit3\|display\[6\]\" is a latch" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 221 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "SW\[2\] " "Info: Assuming node \"SW\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "SW\[1\] " "Info: Assuming node \"SW\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "SW\[8\] " "Info: Assuming node \"SW\[8\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "SW\[4\] " "Info: Assuming node \"SW\[4\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "SW\[0\] " "Info: Assuming node \"SW\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "SW\[5\] " "Info: Assuming node \"SW\[5\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "SW\[6\] " "Info: Assuming node \"SW\[6\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "SW\[7\] " "Info: Assuming node \"SW\[7\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "SW\[3\] " "Info: Assuming node \"SW\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 5 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "9 " "Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "part2:unit1\|mux21:u3\|y~65 " "Info: Detected gated clock \"part2:unit1\|mux21:u3\|y~65\" as buffer" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 108 -1 0 } } { "g:/quartus ii/win/Assignment Editor.qase" "" { Assignment "g:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "part2:unit1\|mux21:u3\|y~65" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "part2:unit1\|mux21:u4\|y~66 " "Info: Detected gated clock \"part2:unit1\|mux21:u4\|y~66\" as buffer" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 108 -1 0 } } { "g:/quartus ii/win/Assignment Editor.qase" "" { Assignment "g:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "part2:unit1\|mux21:u4\|y~66" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "four_bit_adder:add_4bitof2\|f_adder:u3\|d " "Info: Detected gated clock \"four_bit_adder:add_4bitof2\|f_adder:u3\|d\" as buffer" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 179 -1 0 } } { "g:/quartus ii/win/Assignment Editor.qase" "" { Assignment "g:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "four_bit_adder:add_4bitof2\|f_adder:u3\|d" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "part2:unit1\|mux21:u5\|y~13 " "Info: Detected gated clock \"part2:unit1\|mux21:u5\|y~13\" as buffer" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 108 -1 0 } } { "g:/quartus ii/win/Assignment Editor.qase" "" { Assignment "g:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "part2:unit1\|mux21:u5\|y~13" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "four_bit_adder:add_4bitof2\|f_adder:u2\|so~62 " "Info: Detected gated clock \"four_bit_adder:add_4bitof2\|f_adder:u2\|so~62\" as buffer" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } } { "g:/quartus ii/win/Assignment Editor.qase" "" { Assignment "g:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "four_bit_adder:add_4bitof2\|f_adder:u2\|so~62" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "four_bit_adder:add_4bitof2\|f_adder:u4\|co~10 " "Info: Detected gated clock \"four_bit_adder:add_4bitof2\|f_adder:u4\|co~10\" as buffer" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } } { "g:/quartus ii/win/Assignment Editor.qase" "" { Assignment "g:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "four_bit_adder:add_4bitof2\|f_adder:u4\|co~10" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "four_bit_adder:add_4bitof2\|f_adder:u3\|co~123 " "Info: Detected gated clock \"four_bit_adder:add_4bitof2\|f_adder:u3\|co~123\" as buffer" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } } { "g:/quartus ii/win/Assignment Editor.qase" "" { Assignment "g:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "four_bit_adder:add_4bitof2\|f_adder:u3\|co~123" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "four_bit_adder:add_4bitof2\|f_adder:u2\|co~74 " "Info: Detected gated clock \"four_bit_adder:add_4bitof2\|f_adder:u2\|co~74\" as buffer" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } } { "g:/quartus ii/win/Assignment Editor.qase" "" { Assignment "g:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "four_bit_adder:add_4bitof2\|f_adder:u2\|co~74" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "four_bit_adder:add_4bitof2\|f_adder:u1\|co~40 " "Info: Detected gated clock \"four_bit_adder:add_4bitof2\|f_adder:u1\|co~40\" as buffer" {  } { { "part4.vhd" "" { Text "E:/VHDL/实验2/part4/part4.vhd" 176 -1 0 } } { "g:/quartus ii/win/Assignment Editor.qase" "" { Assignment "g:/quartus ii/win/Assignment Editor.qase" 1 { { 0 "four_bit_adder:add_4bitof2\|f_adder:u1\|co~40" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}