part3.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 23 15:47:50 2007 " "Info: Processing started: Wed May 23 15:47:50 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off part3 -c part3 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part3 -c part3 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[0\] Cout 11.040 ns Longest " "Info: Longest tpd from source pin \"b\[0\]\" to destination pin \"Cout\" is 11.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.810 ns) 0.810 ns b\[0\] 1 PIN PIN_G16 2 " "Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_G16; Fanout = 2; PIN Node = 'b\[0\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { b[0] } "NODE_NAME" } } { "part3.vhd" "" { Text "E:/VHDL/实验2/part3/part3.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.284 ns) + CELL(0.150 ns) 6.244 ns f_adder:u1\|co~40 2 COMB LCCOMB_X37_Y35_N22 2 " "Info: 2: + IC(5.284 ns) + CELL(0.150 ns) = 6.244 ns; Loc. = LCCOMB_X37_Y35_N22; Fanout = 2; COMB Node = 'f_adder:u1\|co~40'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.434 ns" { b[0] f_adder:u1|co~40 } "NODE_NAME" } } { "part3.vhd" "" { Text "E:/VHDL/实验2/part3/part3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.150 ns) 6.651 ns f_adder:u2\|co~64 3 COMB LCCOMB_X37_Y35_N2 2 " "Info: 3: + IC(0.257 ns) + CELL(0.150 ns) = 6.651 ns; Loc. = LCCOMB_X37_Y35_N2; Fanout = 2; COMB Node = 'f_adder:u2\|co~64'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.407 ns" { f_adder:u1|co~40 f_adder:u2|co~64 } "NODE_NAME" } } { "part3.vhd" "" { Text "E:/VHDL/实验2/part3/part3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.150 ns) 7.055 ns f_adder:u3\|co~98 4 COMB LCCOMB_X37_Y35_N10 2 " "Info: 4: + IC(0.254 ns) + CELL(0.150 ns) = 7.055 ns; Loc. = LCCOMB_X37_Y35_N10; Fanout = 2; COMB Node = 'f_adder:u3\|co~98'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.404 ns" { f_adder:u2|co~64 f_adder:u3|co~98 } "NODE_NAME" } } { "part3.vhd" "" { Text "E:/VHDL/实验2/part3/part3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.150 ns) 7.452 ns f_adder:u4\|co~10 5 COMB LCCOMB_X37_Y35_N26 1 " "Info: 5: + IC(0.247 ns) + CELL(0.150 ns) = 7.452 ns; Loc. = LCCOMB_X37_Y35_N26; Fanout = 1; COMB Node = 'f_adder:u4\|co~10'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "0.397 ns" { f_adder:u3|co~98 f_adder:u4|co~10 } "NODE_NAME" } } { "part3.vhd" "" { Text "E:/VHDL/实验2/part3/part3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.790 ns) + CELL(2.798 ns) 11.040 ns Cout 6 PIN PIN_A14 0 " "Info: 6: + IC(0.790 ns) + CELL(2.798 ns) = 11.040 ns; Loc. = PIN_A14; Fanout = 0; PIN Node = 'Cout'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.588 ns" { f_adder:u4|co~10 Cout } "NODE_NAME" } } { "part3.vhd" "" { Text "E:/VHDL/实验2/part3/part3.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.208 ns ( 38.12 % ) " "Info: Total cell delay = 4.208 ns ( 38.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.832 ns ( 61.88 % ) " "Info: Total interconnect delay = 6.832 ns ( 61.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "11.040 ns" { b[0] f_adder:u1|co~40 f_adder:u2|co~64 f_adder:u3|co~98 f_adder:u4|co~10 Cout } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "11.040 ns" { b[0] b[0]~combout f_adder:u1|co~40 f_adder:u2|co~64 f_adder:u3|co~98 f_adder:u4|co~10 Cout } { 0.000ns 0.000ns 5.284ns 0.257ns 0.254ns 0.247ns 0.790ns } { 0.000ns 0.810ns 0.150ns 0.150ns 0.150ns 0.150ns 2.798ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 23 15:47:50 2007 " "Info: Processing ended: Wed May 23 15:47:50 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}