part2.hier_info

几个ＶＨＤＬ的编程实例

|part2
V[0] => circuitA:u6.p[0]
V[0] => mux21:u5.a
V[0] => comparator:u1.A[0]
V[1] => circuitA:u6.p[1]
V[1] => mux21:u4.a
V[1] => comparator:u1.A[1]
V[2] => circuitA:u6.p[2]
V[2] => mux21:u3.a
V[2] => comparator:u1.A[2]
V[3] => mux21a:u2.a
V[3] => comparator:u1.A[3]
M[0] <= mux21:u5.y
M[1] <= mux21:u4.y
M[2] <= mux21:u3.y
M[3] <= mux21a:u2.y
z <= comparator:u1.z1


|part2|comparator:u1
A[0] => LessThan0.IN8
A[1] => LessThan0.IN7
A[2] => LessThan0.IN6
A[3] => LessThan0.IN5
z1 <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE


|part2|mux21a:u2
a => y~0.DATAB
s => y~0.OUTPUTSELECT
y <= y~0.DB_MAX_OUTPUT_PORT_TYPE


|part2|mux21:u3
a => y~0.DATAB
d => y~0.DATAA
s => y~0.OUTPUTSELECT
y <= y~0.DB_MAX_OUTPUT_PORT_TYPE


|part2|mux21:u4
a => y~0.DATAB
d => y~0.DATAA
s => y~0.OUTPUTSELECT
y <= y~0.DB_MAX_OUTPUT_PORT_TYPE


|part2|mux21:u5
a => y~0.DATAB
d => y~0.DATAA
s => y~0.OUTPUTSELECT
y <= y~0.DB_MAX_OUTPUT_PORT_TYPE


|part2|circuitA:u6
p[0] => q[0].DATAIN
p[1] => q~0.IN0
p[1] => q[1].DATAIN
p[2] => q~0.IN1
q[0] <= p[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= p[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q~0.DB_MAX_OUTPUT_PORT_TYPE