part2.tan.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 31 15:42:08 2007 " "Info: Processing started: Thu May 31 15:42:08 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off part2 -c part2 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part2 -c part2 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "V\[1\] M\[1\] 10.216 ns Longest " "Info: Longest tpd from source pin \"V\[1\]\" to destination pin \"M\[1\]\" is 10.216 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.860 ns) 0.860 ns V\[1\] 1 PIN PIN_G13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = PIN_G13; Fanout = 4; PIN Node = 'V\[1\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { V[1] } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验2/part2/part2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.305 ns) + CELL(0.437 ns) 6.602 ns mux21:u4\|y~24 2 COMB LCCOMB_X30_Y35_N6 1 " "Info: 2: + IC(5.305 ns) + CELL(0.437 ns) = 6.602 ns; Loc. = LCCOMB_X30_Y35_N6; Fanout = 1; COMB Node = 'mux21:u4\|y~24'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "5.742 ns" { V[1] mux21:u4|y~24 } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验2/part2/part2.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.786 ns) + CELL(2.828 ns) 10.216 ns M\[1\] 3 PIN PIN_J10 0 " "Info: 3: + IC(0.786 ns) + CELL(2.828 ns) = 10.216 ns; Loc. = PIN_J10; Fanout = 0; PIN Node = 'M\[1\]'" {  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.614 ns" { mux21:u4|y~24 M[1] } "NODE_NAME" } } { "part2.vhd" "" { Text "E:/VHDL/实验2/part2/part2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.125 ns ( 40.38 % ) " "Info: Total cell delay = 4.125 ns ( 40.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.091 ns ( 59.62 % ) " "Info: Total interconnect delay = 6.091 ns ( 59.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus ii/win/TimingClosureFloorplan.fld" "" "10.216 ns" { V[1] mux21:u4|y~24 M[1] } "NODE_NAME" } } { "g:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus ii/win/Technology_Viewer.qrui" "10.216 ns" { V[1] V[1]~combout mux21:u4|y~24 M[1] } { 0.000ns 0.000ns 5.305ns 0.786ns } { 0.000ns 0.860ns 0.437ns 2.828ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 31 15:42:08 2007 " "Info: Processing ended: Thu May 31 15:42:08 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}