part2.map.qmsg

几个ＶＨＤＬ的编程实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 31 15:41:41 2007 " "Info: Processing started: Thu May 31 15:41:41 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part2 -c part2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part2 -c part2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "part2.vhd 10 5 " "Warning: Using design file part2.vhd, which is not specified as a design file for the current project, but contains definitions for 10 design units and 5 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 part2-one " "Info: Found design unit 1: part2-one" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验2/part2/part2.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 comparator-Com " "Info: Found design unit 2: comparator-Com" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验2/part2/part2.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 mux21-one " "Info: Found design unit 3: mux21-one" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验2/part2/part2.vhd" 70 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 mux21a-one " "Info: Found design unit 4: mux21a-one" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验2/part2/part2.vhd" 85 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 circuitA-one " "Info: Found design unit 5: circuitA-one" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验2/part2/part2.vhd" 98 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 part2 " "Info: Found entity 1: part2" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验2/part2/part2.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 comparator " "Info: Found entity 2: comparator" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验2/part2/part2.vhd" 49 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 mux21 " "Info: Found entity 3: mux21" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验2/part2/part2.vhd" 65 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 mux21a " "Info: Found entity 4: mux21a" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验2/part2/part2.vhd" 80 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 circuitA " "Info: Found entity 5: circuitA" {  } { { "part2.vhd" "" { Text "E:/VHDL/实验2/part2/part2.vhd" 94 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part2 " "Info: Elaborating entity \"part2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "comparator comparator:u1 " "Info: Elaborating entity \"comparator\" for hierarchy \"comparator:u1\"" {  } { { "part2.vhd" "u1" { Text "E:/VHDL/实验2/part2/part2.vhd" 32 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux21a mux21a:u2 " "Info: Elaborating entity \"mux21a\" for hierarchy \"mux21a:u2\"" {  } { { "part2.vhd" "u2" { Text "E:/VHDL/实验2/part2/part2.vhd" 33 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux21 mux21:u3 " "Info: Elaborating entity \"mux21\" for hierarchy \"mux21:u3\"" {  } { { "part2.vhd" "u3" { Text "E:/VHDL/实验2/part2/part2.vhd" 34 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "circuitA circuitA:u6 " "Info: Elaborating entity \"circuitA\" for hierarchy \"circuitA:u6\"" {  } { { "part2.vhd" "u6" { Text "E:/VHDL/实验2/part2/part2.vhd" 37 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "13 " "Info: Implemented 13 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "4 " "Info: Implemented 4 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 31 15:41:44 2007 " "Info: Processing ended: Thu May 31 15:41:44 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}