sinetest.v

来自「用verilog语言编的正弦波发生器」· Verilog 代码 · 共 32 行

/***********************************************************
 *	File:	sinetest.v
 *	By:	Shuo Huang
 *	Date:	Oct. 30, 2002
 *	Description: This is the test bench for testing the
 *		sine wave generator
 ***********************************************************/

`timescale	1ns / 10ps

module sinetest;
    reg		clk,		// driving clock
		nrst;		// active-low reset
    wire[7:0]	dat;		// sine wave data

    sine gen(.clk(clk), .nrst(nrst), .dout(dat));

    initial begin
	$vcdpluson;
	clk = 0;
	nrst = 0;
	fork
	    forever #10 clk = !clk;
	    begin
		#60 nrst = 1;
		repeat(400) @(posedge clk);
		$finish;
	    end
	join
    end
endmodule