sine.v

来自「用verilog语言编的正弦波发生器」· Verilog 代码 · 共 44 行

/*************************************************************
 *	File:	sine.v
 *	By:	Shuo Huang
 *	Date:	Oct. 30, 2002
 *	Description:	This design generates sine wave in an
 *		8-bit integer format. The output ranges from 0
 *		to 255. Circuit uses a ROM to store one quadrant
 *		sine wave data. There are 64 samples per the
 *		whole cycle of the sine wave.
 **************************************************************/
module sine (clk, nrst, dout);
    input	clk,		// clock input
		nrst;		// active-low reset
    output[7:0]	dout;		// 8-bit output

    reg[3:0]	addr;		// ROM address
    reg[1:0]	quad;		// Quadrant count

    wire[6:0]	d;		// read data from ROM

    rom16x7	rom(.addr(addr), .data(d));

    always @(posedge clk or negedge nrst) begin
	if(!nrst) begin
	    quad <= 0;
	    addr <= 0;
	end
	else begin
	    case (quad)
		0,2: begin
		    if(addr==15) quad <= quad+1;
		    else addr <= addr+1;
		end
		1,3: begin
		    if(addr==0) quad <= quad+1;
		    else addr <= addr-1;
		end
	    endcase
	end
    end

    assign dout = (quad[1])? (128-d):(128+d);
endmodule