latch11.vhd

自己写的锁存器程序

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    14:02:32 05/08/07
-- Design Name:    
-- Module Name:    latch1 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity latch1 is
	PORT(
		clk: in std_logic;
		reset: in std_logic;
--		s: in std_logic;
		d: in std_logic;
		q: out std_logic
		);
end latch1;

architecture Behavioral of latch1 is

--signal s: std_logic_vector(0);

begin

	process(reset, clk, d)
	begin
		
		if reset='0' then
			q<='0';
		elsif falling_edge(clk) and (clk = '0') then
			
			q<=d;

--		else
--			q<=q;	
		end if;
		
	end process;

end Behavioral;