timer_file.vhd

EAS 的接收程序接收来自发射板的RF信号

--//******* File name：timer_file.vhd 
--//******* Function：640KHz time base pulse be divided by 32
--Timing 0.05ms
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity timer_file is 
Port (clk:in std_logic;
   -- end_timer :in std_logic;
    -- synch:in std_logic;
      --timer_begin:in std_logic_vector(2 downto 0);
     -- time_out1:out std_logic_vector(5 downto 0);
      --time_out2:out std_logic_vector(6 downto 0);
      --time_out3:out std_logic_vector(6 downto 0);
      timer : buffer std_logic
      );
end timer_file;
architecture Behavioral of timer_file is
--signal timer1:std_logic_vector(5 downto 0):="0000000";
--signal timer2:std_logic_vector(6 downto 0):="0000000";
--signal timer3:std_logic_vector(6 downto 0):="0000000";
--signal flat :std_logic_vector(1 downto 0);
--signal count2 :std_logic_vector(5 downto 0);

begin
process(clk) --   ,timer_begin,end_timer
--variable count :std_logic_vector(6 downto 0);
variable count1 :std_logic_vector(4 downto 0);
--variable count2 :std_logic_vector(5 downto 0);
--variable count3 :std_logic_vector(6 downto 0);

begin


if  clk'event and clk='1' then
--if timer_begin="001" or timer_begin="010" or timer_begin="100" then
if count1="11111" then
count1:="00000";
timer<=not timer;

else
count1:=count1+1;
end if ;
--end if;


--if end_timer='1' then
--count2<="000000";
--end if;



--case timer_begin is
--when "001"=>
--if timer_begin="001" and timer_begin="010" and timer_begin="100" then
--if count2="111111" then
--  count2<="000000";
--timer1<=timer1+1;
--time_out1<=timer1;
--flat<="01";
--else
--count2<=count2+1;
--end if;
--end if;
--when "010"=>
--elsif end_timer='1' then
--if end_timer='1' then
--count1:="00000";
--end if;

---if count3="1111111" then
--count3:="0000000";
--timer2<=timer2+1;
--flat<="10";
---else
---count3:=count3+1;
---end if;


--when "100"=>
--elsif end_timer='1' then
--if end_timer='1' then
--time_out3<=timer3;
--end if
--if count="1111111" then
--ount:="0000000";
--timer3<=timer3+1;
--flat<="11";
--else
--count:=count+1;
--end if;
--when others =>NULL;
--end case;


--else 
--NULL;
--end if;
end if;
end process;

--process(end_timer)
--begin
--if end_timer='1' then
--if flat="01" then
--time_out1<=timer1;
--elsif flat="01" then
--time_out2<=timer2;
--elsif flat="11" then
--time_out3<=timer3;
--else
--NULL;
--end if;
--end if;
--end process;


--process(clk)
--variable count:std_logic_vector(4 downto 0);
--begin
---if  clk'event and clk='1' then
---if count="11111" then
---count:="00000";
---timer<=not timer;
--else
--count:=count+1;
---end if ;
--end if;


end Behavioral;