receive.vhd

EAS 的接收程序接收来自发射板的RF信号

--// ******************************************************************************* 
--//******* File name：receive.vhd 
--//******* Finaly modify data：2007-04-02
--Author: Xuyou Zou 
--// ******************************************************************************* 
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity receive is 
  Port (clk:in std_logic; --640kHz time base signal;
        trace:in bit; --   trigger sgnal input;
        synch:in std_logic;--synchronization sgnal input;
        green1:out std_logic;
        green2:out std_logic;
        green3:out std_logic; 
        alarm:buffer std_logic   --control sgnal input;
        );  
end receive; 
architecture Behavioral of receive is 
signal c: std_logic_vector(2 downto 0);
--signal d:std_logic_vector(5 downto 0);
--signal e:std_logic_vector(6 downto 0);
--signal f:std_logic_vector(6 downto 0);
signal o :std_logic;
signal g:std_logic;
signal h:std_logic;
--signal i:std_logic;
--signal j: std_logic;

--signal k: std_logic;
--signal l: std_logic;
--signal m: std_logic;

component timer_file
Port (clk:in std_logic;
    --  end_timer :in std_logic;
      --timer_begin:in std_logic_vector(2 downto 0);
     -- time_out1:out std_logic_vector(5 downto 0);
      --time_out2:out std_logic_vector(6 downto 0);
      --time_out3:out std_logic_vector(6 downto 0);
      timer : buffer std_logic
      );

end component;
component synch_file
 Port (synch:in std_logic;--synchronization time
       --temp_in_1:in  std_logic_vector(5 downto 0);
       --temp_in_2:in  std_logic_vector(5 downto 0);
       --temp_in_3:in  std_logic_vector(5 downto 0);
       timer :in std_logic;
       timer_begin:buffer std_logic_vector(2 downto 0);
       flat :buffer std_logic;                ---after synch
       control:out std_logic                --control to alarm
       --start:out std_logic;
       --temp_out_3:out std_logic;
      --end_timer: out std_logic
         ------
         --       count:out 
      );
end component;
--component temp
--port(temp_1 :in std_logic;
 --    temp_2 :in std_logic;
 --    temp_3 :in std_logic;
 ---   judge1:out std_logic;
 --    judge2:out std_logic;
 --    judge3:out std_logic
 --    );
--end component;

component trace_file
 Port (flat:in std_logic;
       clk:in std_logic;
       control:in std_logic;
       timer_begin:in std_logic_vector(2 downto 0);
       timer :in std_logic;
       trace :in bit;
       green1:out std_logic;
       green2:out std_logic;
       green3:out std_logic;
       alarm:buffer std_logic
     );
end component;
begin
u1:timer_file port map(clk,timer=>o);
u2:synch_file port map(synch,timer=>o,timer_begin=>c,flat=>g,control=>h);
--u3:temp       port map(temp_1=>g,temp_2=>h,temp_3=>i,judge1=>k,judge2=>l ,judge3=>m);
u3:trace_file port map(flat=>g,clk,control=>h,timer_begin=>c,timer=>o,trace,green1,green2,green3,alarm);
end Behavioral;