timer.vhd

EAS 的接收程序接收来自发射板的RF信号

--//******* 文件名：receive.vhd 
--//******* 功 能：640KHz时基脉冲32分频
--定时0.05ms
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity timer is 
Port (clk:in std_logic;
      end_timer :in std_logic;
      timer_begin:in std_logic_vector(2 downto 0);
      time_out1:out std_logic_vector(6 downto 0);
      time_out2:out std_logic_vector(6 downto 0);
      time_out3:out std_logic_vector(6 downto 0);
      timer : buffer std_logic
      );
end timer;
architecture Behavioral of timer is
signal timer1:std_logic_vector(6 downto 0):="0000000";
signal timer2:std_logic_vector(6 downto 0):="0000000";
signal timer3:std_logic_vector(6 downto 0):="0000000";

begin
process(clk,timer_begin)    
variable count :std_logic_vector(4 downto 0);
begin
if  clk'event and clk='1' then
--case timer_begin is
--when "001"=>
if timer_begin="001" then

if count="11111" then
count:="00000";
if end_timer='1' then
time_out1<=timer1;
else
timer1<=timer1+1;
end if;
else
count:=count+1;
end if;
--when "010"=>
elsif end_timer='1' then
if count="11111" then
count:="00000";
if timer_begin="000" then
time_out2<=timer2;
else
timer2<=timer2+1;
end if;

else
count:=count+1;
end if;

--when "100"=>
elsif end_timer='1' then
if count="11111" then
count:="00000";
if timer_begin="000" then
time_out3<=timer3;
else
timer3<=timer3+1;
end if;

else
count:=count+1;
end if;
--when others =>NULL;
--end case;
else 
NULL;
end if;
end if;
end process;
process(clk)
variable count:std_logic_vector(4 downto 0);
begin
if  clk'event and clk='1' then
if count="11111" then
count:="00000";
timer<=not timer;
else
count:=count+1;
end if ;
end if;
end process;


end Behavioral;