synch.vhd

EAS 的接收程序接收来自发射板的RF信号

--同步时钟计数
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity synch is 
 Port (synch:in std_logic;
       temp_in_1:in  std_logic_vector(5 downto 0);
       --temp_in_2:in  std_logic_vector(6 downto 0);
       --temp_in_3:in  std_logic_vector(6 downto 0);
       timer_begin:buffer std_logic_vector(2 downto 0);
       temp_out_1:out std_logic;
       --temp_out_2:out std_logic;
      -- temp_out_3:out std_logic;
       end_timer: out std_logic
--       count:out 
      );
end synch;
architecture behavioral of synch is
signal a :std_logic:='0';
begin

p1:process(synch)
variable count :std_logic_vector(1 downto 0);

begin
if  synch'event and synch='1' then
if count="11" then
   count:="00";
else
  count:=count+1;
end if;
end if ;

--case count is
 --when "01"=>
  if rising_edge(synch) then
  if a='0' then 
  a<='1';
  end if;
  end if;
  if a='1'  then 
  if count="01"     then
  timer_begin<="001";
  --end_timer<='1';
   elsif count="10"  then
  timer_begin<="010";
  --end_timer<='1';
   elsif count="11"  then
  timer_begin<="100";
  --end_timer<='1';
  else 
 NULL;
   end if;
   else 
   NULL; 
end if;
--if rising_edge(synch) then
--case count is
--when "01"=>timer_begin<="001";
--when "10"=>timer_begin<="010";
---when "11"=>timer_begin<="100";
---case;
--end if ;


   --if falling_edge(synch)then
   -- timer_begin<="000";
   -- end if;
--when "10"=>
--if rising_edge(synch) then

--end if;
--if falling_edge(synch) then
 --  timer_begin<="000";
--end if;
--when "11"=>
--if rising_edge(synch) then
--timer_begin<="100";
--end if;
--when others =>NULL;
--end case;
if falling_edge(synch) then
 end_timer<='1';
end if;
if timer_begin="001"or timer_begin="010" or timer_begin="100" then
 end_timer<='0';
end if;



temp_out_1<=temp_in_1(1);
--temp_out_2<=temp_in_2(1);
--temp_out_3<=temp_in_3(1);
end process p1;
--process(synch)
--begin
--end process;

end behavioral;