div3.fit.rpt

VHDL实现50％占空比。并且是奇数分频。

+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 3.00) ; Number of LABs  (Total = 6) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 0                           ;
; 2                                          ; 2                           ;
; 3                                          ; 2                           ;
; 4                                          ; 2                           ;
; 5                                          ; 0                           ;
; 6                                          ; 0                           ;
; 7                                          ; 0                           ;
; 8                                          ; 0                           ;
; 9                                          ; 0                           ;
; 10                                         ; 0                           ;
+--------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 1.67) ; Number of LABs  (Total = 6) ;
+------------------------------------+-----------------------------+
; 1 Async. clear                     ; 3                           ;
; 1 Clock                            ; 6                           ;
; 2 Async. clears                    ; 1                           ;
+------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 3.00) ; Number of LABs  (Total = 6) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 2                           ;
; 3                                           ; 2                           ;
; 4                                           ; 2                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 2.00) ; Number of LABs  (Total = 6) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 2                           ;
; 2                                               ; 3                           ;
; 3                                               ; 0                           ;
; 4                                               ; 1                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 2.50) ; Number of LABs  (Total = 6) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
; 2                                           ; 2                           ;
; 3                                           ; 2                           ;
; 4                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Sep 20 21:53:51 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off div3 -c div3
Info: Selected device EP1C3T100C6 for design "div3"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
Info: No exact pin location assignment(s) for 5 pins of 5 total pins
    Info: Pin f not assigned to an exact location on the device
    Info: Pin f1 not assigned to an exact location on the device
    Info: Pin f2 not assigned to an exact location on the device
    Info: Pin f6 not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Automatically promoted signal "clk" to use Global clock in PIN 10
Info: Automatically promoted some destinations of signal "f5~0" to use Global clock
    Info: Destination "f" may be non-global or may not use global clock
Info: Automatically promoted signal "reduce_nor~0" to use Global clock
Info: Automatically promoted signal "reduce_nor~1" to use Global clock
Info: Automatically promoted signal "reduce_nor~2" to use Global clock
Info: Automatically promoted signal "reduce_nor~3" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 4 (unused VREF, 3.30 VCCIO, 0 input, 4 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 1.060 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y5; Fanout = 3; REG Node = 'count1[0]'
    Info: 2: + IC(0.393 ns) + CELL(0.667 ns) = 1.060 ns; Loc. = LAB_X7_Y5; Fanout = 1; REG Node = 'count1[1]'
    Info: Total cell delay = 0.667 ns ( 62.92 % )
    Info: Total interconnect delay = 0.393 ns ( 37.08 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%.
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Node reduce_nor~1 uses non-global routing resources to route signals to global destination nodes
    Info: Port clear -- assigned as a global for destination node f4 -- routed using non-global resources
Info: Node reduce_nor~3 uses non-global routing resources to route signals to global destination nodes
    Info: Port clear -- assigned as a global for destination node f8 -- routed using non-global resources
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Wed Sep 20 21:53:54 2006
    Info: Elapsed time: 00:00:04