div3.fit.qmsg

VHDL实现50％占空比。并且是奇数分频。

{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "4 unused 3.30 0 4 0 " "Info: Number of I/O pins in group: 4 (unused VREF, 3.30 VCCIO, 0 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 11 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 17 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 17 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 17 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.060 ns register register " "Info: Estimated most critical path is register to register delay of 1.060 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count1\[0\] 1 REG LAB_X7_Y5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y5; Fanout = 3; REG Node = 'count1\[0\]'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "" { count1[0] } "NODE_NAME" } "" } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.667 ns) 1.060 ns count1\[1\] 2 REG LAB_X7_Y5 1 " "Info: 2: + IC(0.393 ns) + CELL(0.667 ns) = 1.060 ns; Loc. = LAB_X7_Y5; Fanout = 1; REG Node = 'count1\[1\]'" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "1.060 ns" { count1[0] count1[1] } "NODE_NAME" } "" } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.667 ns 62.92 % " "Info: Total cell delay = 0.667 ns ( 62.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.393 ns 37.08 % " "Info: Total interconnect delay = 0.393 ns ( 37.08 % )" {  } {  } 0}  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "1.060 ns" { count1[0] count1[1] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "reduce_nor~1 " "Info: Node reduce_nor~1 uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear f4 " "Info: Port clear -- assigned as a global for destination node f4 -- routed using non-global resources" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "" { f4 } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "g:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "f4" } } } } { "D:/mypro/div3/div3.fld" "" { Floorplan "D:/mypro/div3/div3.fld" "" "" { f4 } "NODE_NAME" } }  } 0}  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "" { reduce_nor~1 } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "g:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reduce_nor~1" } } } } { "D:/mypro/div3/div3.fld" "" { Floorplan "D:/mypro/div3/div3.fld" "" "" { reduce_nor~1 } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "reduce_nor~3 " "Info: Node reduce_nor~3 uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear f8 " "Info: Port clear -- assigned as a global for destination node f8 -- routed using non-global resources" {  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "" { f8 } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "g:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "f8" } } } } { "div3.vhd" "" { Text "D:/mypro/div3/div3.vhd" 11 -1 0 } } { "D:/mypro/div3/div3.fld" "" { Floorplan "D:/mypro/div3/div3.fld" "" "" { f8 } "NODE_NAME" } }  } 0}  } { { "D:/mypro/div3/db/div3_cmp.qrpt" "" { Report "D:/mypro/div3/db/div3_cmp.qrpt" Compiler "div3" "UNKNOWN" "V1" "D:/mypro/div3/db/div3.quartus_db" { Floorplan "D:/mypro/div3/" "" "" { reduce_nor~3 } "NODE_NAME" } "" } } { "g:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "g:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reduce_nor~3" } } } } { "D:/mypro/div3/div3.fld" "" { Floorplan "D:/mypro/div3/div3.fld" "" "" { reduce_nor~3 } "NODE_NAME" } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 20 21:53:54 2006 " "Info: Processing ended: Wed Sep 20 21:53:54 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}