div3.map.eqn

VHDL实现50％占空比。并且是奇数分频。

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--f3 is f3
--operation mode is normal

f3_lut_out = VCC;
f3 = DFFEAS(f3_lut_out, clk, !A1L42, , , , , , );


--f4 is f4
--operation mode is normal

f4_lut_out = VCC;
f4 = DFFEAS(f4_lut_out, !clk, !A1L52, , , , , , );


--A1L91 is f5~0
--operation mode is normal

A1L91 = !f4 # !f3;


--f7 is f7
--operation mode is normal

f7_lut_out = VCC;
f7 = DFFEAS(f7_lut_out, !A1L91, !A1L62, , , , , , );


--f8 is f8
--operation mode is normal

f8_lut_out = VCC;
f8 = DFFEAS(f8_lut_out, A1L91, !A1L72, , , , , , );


--A1L12 is f6~0
--operation mode is normal

A1L12 = f7 & f8;


--count1[0] is count1[0]
--operation mode is normal

count1[0]_lut_out = !count1[0];
count1[0] = DFFEAS(count1[0]_lut_out, clk, !A1L42, , , , , , );


--count1[1] is count1[1]
--operation mode is normal

count1[1]_lut_out = VCC;
count1[1] = DFFEAS(count1[1]_lut_out, clk, !A1L42, , count1[0], , , , );


--A1L42 is reduce_nor~0
--operation mode is normal

A1L42 = count1[0] & count1[1];


--count2[1] is count2[1]
--operation mode is normal

count2[1]_lut_out = VCC;
count2[1] = DFFEAS(count2[1]_lut_out, !clk, !A1L52, , count2[0], , , , );


--count2[0] is count2[0]
--operation mode is normal

count2[0]_lut_out = !count2[0];
count2[0] = DFFEAS(count2[0]_lut_out, !clk, !A1L52, , , , , , );


--A1L52 is reduce_nor~1
--operation mode is normal

A1L52 = count2[1] & count2[0];


--count3[1] is count3[1]
--operation mode is normal

count3[1]_lut_out = VCC;
count3[1] = DFFEAS(count3[1]_lut_out, !A1L91, !A1L62, , count3[0], , , , );


--count3[0] is count3[0]
--operation mode is normal

count3[0]_lut_out = !count3[0];
count3[0] = DFFEAS(count3[0]_lut_out, !A1L91, !A1L62, , , , , , );


--A1L62 is reduce_nor~2
--operation mode is normal

A1L62 = count3[1] & count3[0];


--count4[1] is count4[1]
--operation mode is normal

count4[1]_lut_out = VCC;
count4[1] = DFFEAS(count4[1]_lut_out, A1L91, !A1L72, , count4[0], , , , );


--count4[0] is count4[0]
--operation mode is normal

count4[0]_lut_out = !count4[0];
count4[0] = DFFEAS(count4[0]_lut_out, A1L91, !A1L72, , , , , , );


--A1L72 is reduce_nor~3
--operation mode is normal

A1L72 = count4[1] & count4[0];


--clk is clk
--operation mode is input

clk = INPUT();


--f is f
--operation mode is output

f = OUTPUT(!A1L91);


--f1 is f1
--operation mode is output

f1 = OUTPUT(f3);


--f2 is f2
--operation mode is output

f2 = OUTPUT(f4);


--f6 is f6
--operation mode is output

f6 = OUTPUT(A1L12);