div3.map.summary

VHDL实现50％占空比。并且是奇数分频。

Flow Status : Successful - Wed Sep 20 21:53:48 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : div3
Top-level Entity Name : div3
Family : Cyclone
Device : EP1C3T100C6
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 18
Total pins : 5
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0