ad9851.tan.summary

用VHDL语言编写的DDS正弦函数发生器

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 9.541 ns
From           : MPF[1]
To             : AD9851:inst2|DATA_TEMP[24]
From Clock     : --
To Clock       : MCU_CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.727 ns
From           : AD9851:inst2|W_CLK
To             : W_CLK
From Clock     : SYS_CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.818 ns
From           : MPF[0]
To             : AD9851:inst2|DATA_TEMP[34]
From Clock     : --
To Clock       : MCU_CLK
Failed Paths   : 0

Type           : Clock Setup: 'SYS_CLK'
Slack          : 14.578 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 184.43 MHz ( period = 5.422 ns )
From           : AD9851:inst2|STAT[1]
To             : AD9851:inst2|DAT_OUT[0]
From Clock     : SYS_CLK
To Clock       : SYS_CLK
Failed Paths   : 0

Type           : Clock Setup: 'MCU_CLK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : AD9851:inst2|DATA_TEMP[24]
To             : AD9851:inst2|DATA_TEMP[32]
From Clock     : MCU_CLK
To Clock       : MCU_CLK
Failed Paths   : 0

Type           : Clock Hold: 'SYS_CLK'
Slack          : -2.461 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : JUDGE:JUDGE|TEMP[0]
To             : FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0
From Clock     : SYS_CLK
To Clock       : SYS_CLK
Failed Paths   : 16

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 16

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