fre.vhd

用VHDL语言编写的DDS正弦函数发生器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FRE IS
	PORT(SYS_CLK:IN STD_LOGIC;
	 	 CLK_25M:OUT STD_LOGIC);
END;
ARCHITECTURE ONE OF FRE IS
	SIGNAL F:STD_LOGIC_VECTOR(2 DOWNTO 0);
	BEGIN
	CLK_25M<=F(1);
	PROCESS(SYS_CLK)
		BEGIN
		IF SYS_CLK'EVENT AND SYS_CLK='1' THEN
			F<=F+1;
		END IF;
	END PROCESS;
END;