ad9851.hier_info

用VHDL语言编写的DDS正弦函数发生器

FM_EN => DATA_TEMP[14].ALOAD
FM_EN => DATA_TEMP[15].ALOAD
FM_EN => DATA_TEMP[16].ALOAD
FM_EN => DATA_TEMP[17].ALOAD
FM_EN => DATA_TEMP[18].ALOAD
FM_EN => DATA_TEMP[19].ALOAD
FM_EN => DATA_TEMP[20].ALOAD
FM_EN => DATA_TEMP[21].ALOAD
FM_EN => DATA_TEMP[22].ALOAD
FM_EN => DATA_TEMP[23].ALOAD
FM_EN => DATA_TEMP[24].ALOAD
FM_EN => DATA_TEMP[25].ALOAD
FM_EN => DATA_TEMP[26].ALOAD
FM_EN => DATA_TEMP[27].ALOAD
FM_EN => DATA_TEMP[28].ALOAD
FM_EN => DATA_TEMP[29].ALOAD
FM_EN => DATA_TEMP[30].ALOAD
FM_EN => DATA_TEMP[31].ALOAD
FM_EN => DATA_TEMP[32].PRESET
FM_EN => DATA_TEMP[33].ACLR
FM_EN => DATA_TEMP[34].ACLR
FM_EN => DATA_TEMP[35].ACLR
FM_EN => DATA_TEMP[36].ACLR
FM_EN => DATA_TEMP[37].ACLR
FM_EN => DATA_TEMP[38].ACLR
FM_EN => DATA_TEMP[39].ACLR
FM_EN => COTR[0].ALOAD
FM_EN => COTR[1].ALOAD
FM_EN => COTR[2].ALOAD
MPF[0] => Equal0.IN3
MPF[0] => Equal1.IN3
MPF[0] => Equal2.IN3
MPF[1] => Equal0.IN2
MPF[1] => Equal1.IN2
MPF[1] => Equal2.IN2
FM_DATA[0] => DATA_TEMP[0].ADATA
FM_DATA[1] => DATA_TEMP[1].ADATA
FM_DATA[2] => DATA_TEMP[2].ADATA
FM_DATA[3] => DATA_TEMP[3].ADATA
FM_DATA[4] => DATA_TEMP[4].ADATA
FM_DATA[5] => DATA_TEMP[5].ADATA
FM_DATA[6] => DATA_TEMP[6].ADATA
FM_DATA[7] => DATA_TEMP[7].ADATA
FM_DATA[8] => DATA_TEMP[8].ADATA
FM_DATA[9] => DATA_TEMP[9].ADATA
FM_DATA[10] => DATA_TEMP[10].ADATA
FM_DATA[11] => DATA_TEMP[11].ADATA
FM_DATA[12] => DATA_TEMP[12].ADATA
FM_DATA[13] => DATA_TEMP[13].ADATA
FM_DATA[14] => DATA_TEMP[14].ADATA
FM_DATA[15] => DATA_TEMP[15].ADATA
FM_DATA[16] => DATA_TEMP[16].ADATA
FM_DATA[17] => DATA_TEMP[17].ADATA
FM_DATA[18] => DATA_TEMP[18].ADATA
FM_DATA[19] => DATA_TEMP[19].ADATA
FM_DATA[20] => DATA_TEMP[20].ADATA
FM_DATA[21] => DATA_TEMP[21].ADATA
FM_DATA[22] => DATA_TEMP[22].ADATA
FM_DATA[23] => DATA_TEMP[23].ADATA
FM_DATA[24] => DATA_TEMP[24].ADATA
FM_DATA[25] => DATA_TEMP[25].ADATA
FM_DATA[26] => DATA_TEMP[26].ADATA
FM_DATA[27] => DATA_TEMP[27].ADATA
FM_DATA[28] => DATA_TEMP[28].ADATA
FM_DATA[29] => DATA_TEMP[29].ADATA
FM_DATA[30] => DATA_TEMP[30].ADATA
FM_DATA[31] => DATA_TEMP[31].ADATA
FM_CORT[0] => COTR[0].ADATA
FM_CORT[1] => COTR[1].ADATA
FM_CORT[2] => COTR[2].ADATA
DAT_IN[0] => COTR~2.DATAB
DAT_IN[0] => DATA_TEMP~129.DATAB
DAT_IN[0] => COTR~8.DATAB
DAT_IN[0] => COTR~11.DATAB
DAT_IN[1] => COTR~1.DATAB
DAT_IN[1] => DATA_TEMP~128.DATAB
DAT_IN[1] => COTR~7.DATAB
DAT_IN[1] => COTR~10.DATAB
DAT_IN[2] => COTR~0.DATAB
DAT_IN[2] => DATA_TEMP~127.DATAB
DAT_IN[2] => COTR~6.DATAB
DAT_IN[2] => COTR~9.DATAB
DAT_IN[3] => DATA_TEMP~126.DATAB
DAT_IN[4] => DATA_TEMP~125.DATAB
DAT_IN[5] => DATA_TEMP~124.DATAB
DAT_IN[6] => DATA_TEMP~123.DATAB
DAT_IN[7] => DATA_TEMP~122.DATAB
DAT_OUT[0] <= DAT_OUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[1] <= DAT_OUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[2] <= DAT_OUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[3] <= DAT_OUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[4] <= DAT_OUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[5] <= DAT_OUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[6] <= DAT_OUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[7] <= DAT_OUT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
REST <= REST~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQ_UD <= FQ_UD~reg0.DB_MAX_OUTPUT_PORT_TYPE
W_CLK <= W_CLK~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SYS_TOP|JUDGE:JUDGE
DAT_IN[0] => Equal0.IN7
DAT_IN[0] => TEMP[0].DATAIN
DAT_IN[0] => DAT_OUT[0]~reg0.DATAIN
DAT_IN[1] => Equal0.IN6
DAT_IN[1] => TEMP[1].DATAIN
DAT_IN[1] => DAT_OUT[1]~reg0.DATAIN
DAT_IN[2] => Equal0.IN5
DAT_IN[2] => TEMP[2].DATAIN
DAT_IN[2] => DAT_OUT[2]~reg0.DATAIN
DAT_IN[3] => Equal0.IN4
DAT_IN[3] => TEMP[3].DATAIN
DAT_IN[3] => DAT_OUT[3]~reg0.DATAIN
DAT_IN[4] => Equal0.IN3
DAT_IN[4] => TEMP[4].DATAIN
DAT_IN[4] => DAT_OUT[4]~reg0.DATAIN
DAT_IN[5] => Equal0.IN2
DAT_IN[5] => TEMP[5].DATAIN
DAT_IN[5] => DAT_OUT[5]~reg0.DATAIN
DAT_IN[6] => Equal0.IN1
DAT_IN[6] => TEMP[6].DATAIN
DAT_IN[6] => DAT_OUT[6]~reg0.DATAIN
DAT_IN[7] => Equal0.IN0
DAT_IN[7] => TEMP[7].DATAIN
DAT_IN[7] => DAT_OUT[7]~reg0.DATAIN
SYS_CLK => TEMP[0].CLK
SYS_CLK => TEMP[1].CLK
SYS_CLK => TEMP[2].CLK
SYS_CLK => TEMP[3].CLK
SYS_CLK => TEMP[4].CLK
SYS_CLK => TEMP[5].CLK
SYS_CLK => TEMP[6].CLK
SYS_CLK => TEMP[7].CLK
SYS_CLK => FM_CORT[0]~reg0.CLK
SYS_CLK => FM_CORT[1]~reg0.CLK
SYS_CLK => FM_CORT[2]~reg0.CLK
SYS_CLK => DAT_OUT[0]~reg0.CLK
SYS_CLK => DAT_OUT[1]~reg0.CLK
SYS_CLK => DAT_OUT[2]~reg0.CLK
SYS_CLK => DAT_OUT[3]~reg0.CLK
SYS_CLK => DAT_OUT[4]~reg0.CLK
SYS_CLK => DAT_OUT[5]~reg0.CLK
SYS_CLK => DAT_OUT[6]~reg0.CLK
SYS_CLK => DAT_OUT[7]~reg0.CLK
SYS_CLK => ROM_CLK~reg0.CLK
DAT_OUT[0] <= DAT_OUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[1] <= DAT_OUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[2] <= DAT_OUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[3] <= DAT_OUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[4] <= DAT_OUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[5] <= DAT_OUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[6] <= DAT_OUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT_OUT[7] <= DAT_OUT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ROM_CLK <= ROM_CLK~reg0.DB_MAX_OUTPUT_PORT_TYPE
FM_CORT[0] <= FM_CORT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FM_CORT[1] <= FM_CORT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FM_CORT[2] <= FM_CORT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SYS_TOP|FM:ROM
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]
q[10] <= altsyncram:altsyncram_component.q_a[10]
q[11] <= altsyncram:altsyncram_component.q_a[11]
q[12] <= altsyncram:altsyncram_component.q_a[12]
q[13] <= altsyncram:altsyncram_component.q_a[13]
q[14] <= altsyncram:altsyncram_component.q_a[14]
q[15] <= altsyncram:altsyncram_component.q_a[15]
q[16] <= altsyncram:altsyncram_component.q_a[16]
q[17] <= altsyncram:altsyncram_component.q_a[17]
q[18] <= altsyncram:altsyncram_component.q_a[18]
q[19] <= altsyncram:altsyncram_component.q_a[19]
q[20] <= altsyncram:altsyncram_component.q_a[20]
q[21] <= altsyncram:altsyncram_component.q_a[21]
q[22] <= altsyncram:altsyncram_component.q_a[22]
q[23] <= altsyncram:altsyncram_component.q_a[23]
q[24] <= altsyncram:altsyncram_component.q_a[24]
q[25] <= altsyncram:altsyncram_component.q_a[25]
q[26] <= altsyncram:altsyncram_component.q_a[26]
q[27] <= altsyncram:altsyncram_component.q_a[27]
q[28] <= altsyncram:altsyncram_component.q_a[28]
q[29] <= altsyncram:altsyncram_component.q_a[29]
q[30] <= altsyncram:altsyncram_component.q_a[30]
q[31] <= altsyncram:altsyncram_component.q_a[31]


|SYS_TOP|FM:ROM|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_a[16] => ~NO_FANOUT~
data_a[17] => ~NO_FANOUT~
data_a[18] => ~NO_FANOUT~
data_a[19] => ~NO_FANOUT~
data_a[20] => ~NO_FANOUT~
data_a[21] => ~NO_FANOUT~
data_a[22] => ~NO_FANOUT~
data_a[23] => ~NO_FANOUT~
data_a[24] => ~NO_FANOUT~
data_a[25] => ~NO_FANOUT~
data_a[26] => ~NO_FANOUT~
data_a[27] => ~NO_FANOUT~
data_a[28] => ~NO_FANOUT~
data_a[29] => ~NO_FANOUT~
data_a[30] => ~NO_FANOUT~
data_a[31] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_jm21:auto_generated.address_a[0]
address_a[1] => altsyncram_jm21:auto_generated.address_a[1]
address_a[2] => altsyncram_jm21:auto_generated.address_a[2]
address_a[3] => altsyncram_jm21:auto_generated.address_a[3]
address_a[4] => altsyncram_jm21:auto_generated.address_a[4]
address_a[5] => altsyncram_jm21:auto_generated.address_a[5]
address_a[6] => altsyncram_jm21:auto_generated.address_a[6]
address_a[7] => altsyncram_jm21:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_jm21:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_jm21:auto_generated.q_a[0]
q_a[1] <= altsyncram_jm21:auto_generated.q_a[1]
q_a[2] <= altsyncram_jm21:auto_generated.q_a[2]
q_a[3] <= altsyncram_jm21:auto_generated.q_a[3]
q_a[4] <= altsyncram_jm21:auto_generated.q_a[4]
q_a[5] <= altsyncram_jm21:auto_generated.q_a[5]
q_a[6] <= altsyncram_jm21:auto_generated.q_a[6]
q_a[7] <= altsyncram_jm21:auto_generated.q_a[7]
q_a[8] <= altsyncram_jm21:auto_generated.q_a[8]
q_a[9] <= altsyncram_jm21:auto_generated.q_a[9]
q_a[10] <= altsyncram_jm21:auto_generated.q_a[10]
q_a[11] <= altsyncram_jm21:auto_generated.q_a[11]
q_a[12] <= altsyncram_jm21:auto_generated.q_a[12]
q_a[13] <= altsyncram_jm21:auto_generated.q_a[13]
q_a[14] <= altsyncram_jm21:auto_generated.q_a[14]
q_a[15] <= altsyncram_jm21:auto_generated.q_a[15]
q_a[16] <= altsyncram_jm21:auto_generated.q_a[16]
q_a[17] <= altsyncram_jm21:auto_generated.q_a[17]
q_a[18] <= altsyncram_jm21:auto_generated.q_a[18]
q_a[19] <= altsyncram_jm21:auto_generated.q_a[19]
q_a[20] <= altsyncram_jm21:auto_generated.q_a[20]
q_a[21] <= altsyncram_jm21:auto_generated.q_a[21]
q_a[22] <= altsyncram_jm21:auto_generated.q_a[22]
q_a[23] <= altsyncram_jm21:auto_generated.q_a[23]
q_a[24] <= altsyncram_jm21:auto_generated.q_a[24]
q_a[25] <= altsyncram_jm21:auto_generated.q_a[25]
q_a[26] <= altsyncram_jm21:auto_generated.q_a[26]
q_a[27] <= altsyncram_jm21:auto_generated.q_a[27]
q_a[28] <= altsyncram_jm21:auto_generated.q_a[28]
q_a[29] <= altsyncram_jm21:auto_generated.q_a[29]
q_a[30] <= altsyncram_jm21:auto_generated.q_a[30]
q_a[31] <= altsyncram_jm21:auto_generated.q_a[31]
q_b[0] <= <GND>


|SYS_TOP|FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR