ad9851.tan.qmsg

用VHDL语言编写的DDS正弦函数发生器

{ "Info" "ITDB_TSU_RESULT" "AD9851:inst2\|DATA_TEMP\[16\] MPF\[1\] MCU_CLK 9.541 ns register " "Info: tsu for register \"AD9851:inst2\|DATA_TEMP\[16\]\" (data pin = \"MPF\[1\]\", clock pin = \"MCU_CLK\") is 9.541 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.162 ns + Longest pin register " "Info: + Longest pin to register delay is 12.162 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MPF\[1\] 1 PIN PIN_26 44 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_26; Fanout = 44; PIN Node = 'MPF\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { MPF[1] } "NODE_NAME" } } { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 304 -280 -112 320 "MPF\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.585 ns) + CELL(0.442 ns) 9.496 ns AD9851:inst2\|DATA_TEMP\[3\]~2449 2 COMB LC_X11_Y9_N4 31 " "Info: 2: + IC(7.585 ns) + CELL(0.442 ns) = 9.496 ns; Loc. = LC_X11_Y9_N4; Fanout = 31; COMB Node = 'AD9851:inst2\|DATA_TEMP\[3\]~2449'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.027 ns" { MPF[1] AD9851:inst2|DATA_TEMP[3]~2449 } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.799 ns) + CELL(0.867 ns) 12.162 ns AD9851:inst2\|DATA_TEMP\[16\] 3 REG LC_X15_Y7_N3 2 " "Info: 3: + IC(1.799 ns) + CELL(0.867 ns) = 12.162 ns; Loc. = LC_X15_Y7_N3; Fanout = 2; REG Node = 'AD9851:inst2\|DATA_TEMP\[16\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.666 ns" { AD9851:inst2|DATA_TEMP[3]~2449 AD9851:inst2|DATA_TEMP[16] } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.778 ns ( 22.84 % ) " "Info: Total cell delay = 2.778 ns ( 22.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.384 ns ( 77.16 % ) " "Info: Total interconnect delay = 9.384 ns ( 77.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.162 ns" { MPF[1] AD9851:inst2|DATA_TEMP[3]~2449 AD9851:inst2|DATA_TEMP[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.162 ns" { MPF[1] MPF[1]~out0 AD9851:inst2|DATA_TEMP[3]~2449 AD9851:inst2|DATA_TEMP[16] } { 0.000ns 0.000ns 7.585ns 1.799ns } { 0.000ns 1.469ns 0.442ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MCU_CLK destination 2.658 ns - Shortest register " "Info: - Shortest clock path from clock \"MCU_CLK\" to destination register is 2.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MCU_CLK 1 CLK PIN_28 43 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 43; CLK Node = 'MCU_CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { MCU_CLK } "NODE_NAME" } } { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 256 -280 -112 272 "MCU_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.478 ns) + CELL(0.711 ns) 2.658 ns AD9851:inst2\|DATA_TEMP\[16\] 2 REG LC_X15_Y7_N3 2 " "Info: 2: + IC(0.478 ns) + CELL(0.711 ns) = 2.658 ns; Loc. = LC_X15_Y7_N3; Fanout = 2; REG Node = 'AD9851:inst2\|DATA_TEMP\[16\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.189 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[16] } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 82.02 % ) " "Info: Total cell delay = 2.180 ns ( 82.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.478 ns ( 17.98 % ) " "Info: Total interconnect delay = 0.478 ns ( 17.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.658 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.658 ns" { MCU_CLK MCU_CLK~out0 AD9851:inst2|DATA_TEMP[16] } { 0.000ns 0.000ns 0.478ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.162 ns" { MPF[1] AD9851:inst2|DATA_TEMP[3]~2449 AD9851:inst2|DATA_TEMP[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.162 ns" { MPF[1] MPF[1]~out0 AD9851:inst2|DATA_TEMP[3]~2449 AD9851:inst2|DATA_TEMP[16] } { 0.000ns 0.000ns 7.585ns 1.799ns } { 0.000ns 1.469ns 0.442ns 0.867ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.658 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[16] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.658 ns" { MCU_CLK MCU_CLK~out0 AD9851:inst2|DATA_TEMP[16] } { 0.000ns 0.000ns 0.478ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SYS_CLK W_CLK AD9851:inst2\|W_CLK 7.727 ns register " "Info: tco from clock \"SYS_CLK\" to destination pin \"W_CLK\" through register \"AD9851:inst2\|W_CLK\" is 7.727 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK source 2.782 ns + Longest register " "Info: + Longest clock path from clock \"SYS_CLK\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_93 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 25; CLK Node = 'SYS_CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SYS_CLK } "NODE_NAME" } } { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 144 -280 -112 160 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns AD9851:inst2\|W_CLK 2 REG LC_X15_Y6_N6 5 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y6_N6; Fanout = 5; REG Node = 'AD9851:inst2\|W_CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { SYS_CLK AD9851:inst2|W_CLK } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { SYS_CLK AD9851:inst2|W_CLK } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { SYS_CLK SYS_CLK~out0 AD9851:inst2|W_CLK } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.721 ns + Longest register pin " "Info: + Longest register to pin delay is 4.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AD9851:inst2\|W_CLK 1 REG LC_X15_Y6_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y6_N6; Fanout = 5; REG Node = 'AD9851:inst2\|W_CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AD9851:inst2|W_CLK } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.613 ns) + CELL(2.108 ns) 4.721 ns W_CLK 2 PIN PIN_59 0 " "Info: 2: + IC(2.613 ns) + CELL(2.108 ns) = 4.721 ns; Loc. = PIN_59; Fanout = 0; PIN Node = 'W_CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.721 ns" { AD9851:inst2|W_CLK W_CLK } "NODE_NAME" } } { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 192 936 1112 208 "W_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 44.65 % ) " "Info: Total cell delay = 2.108 ns ( 44.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.613 ns ( 55.35 % ) " "Info: Total interconnect delay = 2.613 ns ( 55.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.721 ns" { AD9851:inst2|W_CLK W_CLK } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.721 ns" { AD9851:inst2|W_CLK W_CLK } { 0.000ns 2.613ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { SYS_CLK AD9851:inst2|W_CLK } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { SYS_CLK SYS_CLK~out0 AD9851:inst2|W_CLK } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.721 ns" { AD9851:inst2|W_CLK W_CLK } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.721 ns" { AD9851:inst2|W_CLK W_CLK } { 0.000ns 2.613ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "AD9851:inst2\|DATA_TEMP\[34\] MPF\[0\] MCU_CLK -0.818 ns register " "Info: th for register \"AD9851:inst2\|DATA_TEMP\[34\]\" (data pin = \"MPF\[0\]\", clock pin = \"MCU_CLK\") is -0.818 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MCU_CLK destination 2.616 ns + Longest register " "Info: + Longest clock path from clock \"MCU_CLK\" to destination register is 2.616 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MCU_CLK 1 CLK PIN_28 43 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 43; CLK Node = 'MCU_CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { MCU_CLK } "NODE_NAME" } } { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 256 -280 -112 272 "MCU_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.711 ns) 2.616 ns AD9851:inst2\|DATA_TEMP\[34\] 2 REG LC_X11_Y7_N4 1 " "Info: 2: + IC(0.436 ns) + CELL(0.711 ns) = 2.616 ns; Loc. = LC_X11_Y7_N4; Fanout = 1; REG Node = 'AD9851:inst2\|DATA_TEMP\[34\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.147 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[34] } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 83.33 % ) " "Info: Total cell delay = 2.180 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.436 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.436 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.616 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[34] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.616 ns" { MCU_CLK MCU_CLK~out0 AD9851:inst2|DATA_TEMP[34] } { 0.000ns 0.000ns 0.436ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.449 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.449 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MPF\[0\] 1 PIN PIN_17 43 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 43; PIN Node = 'MPF\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { MPF[0] } "NODE_NAME" } } { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 304 -280 -112 320 "MPF\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.502 ns) + CELL(0.478 ns) 3.449 ns AD9851:inst2\|DATA_TEMP\[34\] 2 REG LC_X11_Y7_N4 1 " "Info: 2: + IC(1.502 ns) + CELL(0.478 ns) = 3.449 ns; Loc. = LC_X11_Y7_N4; Fanout = 1; REG Node = 'AD9851:inst2\|DATA_TEMP\[34\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.980 ns" { MPF[0] AD9851:inst2|DATA_TEMP[34] } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns ( 56.45 % ) " "Info: Total cell delay = 1.947 ns ( 56.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.502 ns ( 43.55 % ) " "Info: Total interconnect delay = 1.502 ns ( 43.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.449 ns" { MPF[0] AD9851:inst2|DATA_TEMP[34] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.449 ns" { MPF[0] MPF[0]~out0 AD9851:inst2|DATA_TEMP[34] } { 0.000ns 0.000ns 1.502ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.616 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[34] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.616 ns" { MCU_CLK MCU_CLK~out0 AD9851:inst2|DATA_TEMP[34] } { 0.000ns 0.000ns 0.436ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.449 ns" { MPF[0] AD9851:inst2|DATA_TEMP[34] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.449 ns" { MPF[0] MPF[0]~out0 AD9851:inst2|DATA_TEMP[34] } { 0.000ns 0.000ns 1.502ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}