📄 ad9851.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "MCU_CLK register register AD9851:inst2\|DATA_TEMP\[24\] AD9851:inst2\|DATA_TEMP\[32\] 275.03 MHz Internal " "Info: Clock \"MCU_CLK\" Internal fmax is restricted to 275.03 MHz between source register \"AD9851:inst2\|DATA_TEMP\[24\]\" and destination register \"AD9851:inst2\|DATA_TEMP\[32\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.909 ns + Longest register register " "Info: + Longest register to register delay is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AD9851:inst2\|DATA_TEMP\[24\] 1 REG LC_X15_Y7_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y7_N4; Fanout = 2; REG Node = 'AD9851:inst2\|DATA_TEMP\[24\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AD9851:inst2|DATA_TEMP[24] } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.518 ns) + CELL(0.442 ns) 0.960 ns AD9851:inst2\|DATA_TEMP\[32\]~2487 2 COMB LC_X15_Y7_N2 1 " "Info: 2: + IC(0.518 ns) + CELL(0.442 ns) = 0.960 ns; Loc. = LC_X15_Y7_N2; Fanout = 1; COMB Node = 'AD9851:inst2\|DATA_TEMP\[32\]~2487'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.960 ns" { AD9851:inst2|DATA_TEMP[24] AD9851:inst2|DATA_TEMP[32]~2487 } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.211 ns) + CELL(0.738 ns) 2.909 ns AD9851:inst2\|DATA_TEMP\[32\] 3 REG LC_X15_Y8_N8 2 " "Info: 3: + IC(1.211 ns) + CELL(0.738 ns) = 2.909 ns; Loc. = LC_X15_Y8_N8; Fanout = 2; REG Node = 'AD9851:inst2\|DATA_TEMP\[32\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.949 ns" { AD9851:inst2|DATA_TEMP[32]~2487 AD9851:inst2|DATA_TEMP[32] } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.180 ns ( 40.56 % ) " "Info: Total cell delay = 1.180 ns ( 40.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.729 ns ( 59.44 % ) " "Info: Total interconnect delay = 1.729 ns ( 59.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { AD9851:inst2|DATA_TEMP[24] AD9851:inst2|DATA_TEMP[32]~2487 AD9851:inst2|DATA_TEMP[32] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { AD9851:inst2|DATA_TEMP[24] AD9851:inst2|DATA_TEMP[32]~2487 AD9851:inst2|DATA_TEMP[32] } { 0.000ns 0.518ns 1.211ns } { 0.000ns 0.442ns 0.738ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MCU_CLK destination 2.658 ns + Shortest register " "Info: + Shortest clock path from clock \"MCU_CLK\" to destination register is 2.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MCU_CLK 1 CLK PIN_28 43 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 43; CLK Node = 'MCU_CLK'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { MCU_CLK } "NODE_NAME" } } { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 256 -280 -112 272 "MCU_CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.478 ns) + CELL(0.711 ns) 2.658 ns AD9851:inst2\|DATA_TEMP\[32\] 2 REG LC_X15_Y8_N8 2 " "Info: 2: + IC(0.478 ns) + CELL(0.711 ns) = 2.658 ns; Loc. = LC_X15_Y8_N8; Fanout = 2; REG Node = 'AD9851:inst2\|DATA_TEMP\[32\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.189 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[32] } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 82.02 % ) " "Info: Total cell delay = 2.180 ns ( 82.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.478 ns ( 17.98 % ) " "Info: Total interconnect delay = 0.478 ns ( 17.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.658 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[32] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.658 ns" { MCU_CLK MCU_CLK~out0 AD9851:inst2|DATA_TEMP[32] } { 0.000ns 0.000ns 0.478ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MCU_CLK source 2.658 ns - Longest register " "Info: - Longest clock path from clock \"MCU_CLK\" to source register is 2.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MCU_CLK 1 CLK PIN_28 43 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 43; CLK Node = 'MCU_CLK'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { MCU_CLK } "NODE_NAME" } } { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 256 -280 -112 272 "MCU_CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.478 ns) + CELL(0.711 ns) 2.658 ns AD9851:inst2\|DATA_TEMP\[24\] 2 REG LC_X15_Y7_N4 2 " "Info: 2: + IC(0.478 ns) + CELL(0.711 ns) = 2.658 ns; Loc. = LC_X15_Y7_N4; Fanout = 2; REG Node = 'AD9851:inst2\|DATA_TEMP\[24\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.189 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[24] } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 82.02 % ) " "Info: Total cell delay = 2.180 ns ( 82.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.478 ns ( 17.98 % ) " "Info: Total interconnect delay = 0.478 ns ( 17.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.658 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.658 ns" { MCU_CLK MCU_CLK~out0 AD9851:inst2|DATA_TEMP[24] } { 0.000ns 0.000ns 0.478ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.658 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[32] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.658 ns" { MCU_CLK MCU_CLK~out0 AD9851:inst2|DATA_TEMP[32] } { 0.000ns 0.000ns 0.478ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.658 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.658 ns" { MCU_CLK MCU_CLK~out0 AD9851:inst2|DATA_TEMP[24] } { 0.000ns 0.000ns 0.478ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { AD9851:inst2|DATA_TEMP[24] AD9851:inst2|DATA_TEMP[32]~2487 AD9851:inst2|DATA_TEMP[32] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { AD9851:inst2|DATA_TEMP[24] AD9851:inst2|DATA_TEMP[32]~2487 AD9851:inst2|DATA_TEMP[32] } { 0.000ns 0.518ns 1.211ns } { 0.000ns 0.442ns 0.738ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.658 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[32] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.658 ns" { MCU_CLK MCU_CLK~out0 AD9851:inst2|DATA_TEMP[32] } { 0.000ns 0.000ns 0.478ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.658 ns" { MCU_CLK AD9851:inst2|DATA_TEMP[24] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.658 ns" { MCU_CLK MCU_CLK~out0 AD9851:inst2|DATA_TEMP[24] } { 0.000ns 0.000ns 0.478ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AD9851:inst2|DATA_TEMP[32] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { AD9851:inst2|DATA_TEMP[32] } { } { } } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "SYS_CLK register JUDGE:JUDGE\|TEMP\[0\] memory FM:ROM\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|ram_block1a7~porta_address_reg0 -2.461 ns " "Info: Minimum slack time is -2.461 ns for clock \"SYS_CLK\" between source register \"JUDGE:JUDGE\|TEMP\[0\]\" and destination memory \"FM:ROM\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|ram_block1a7~porta_address_reg0\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.230 ns + Shortest register memory " "Info: + Shortest register to memory delay is 2.230 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns JUDGE:JUDGE\|TEMP\[0\] 1 REG LC_X11_Y6_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y6_N9; Fanout = 3; REG Node = 'JUDGE:JUDGE\|TEMP\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { JUDGE:JUDGE|TEMP[0] } "NODE_NAME" } } { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.847 ns) + CELL(0.383 ns) 2.230 ns FM:ROM\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|ram_block1a7~porta_address_reg0 2 MEM M4K_X13_Y8 18 " "Info: 2: + IC(1.847 ns) + CELL(0.383 ns) = 2.230 ns; Loc. = M4K_X13_Y8; Fanout = 18; MEM Node = 'FM:ROM\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|ram_block1a7~porta_address_reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.230 ns" { JUDGE:JUDGE|TEMP[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_jm21.tdf" "" { Text "E:/my project/quartusII/AD9851/db/altsyncram_jm21.tdf" 183 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.383 ns ( 17.17 % ) " "Info: Total cell delay = 0.383 ns ( 17.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.847 ns ( 82.83 % ) " "Info: Total interconnect delay = 1.847 ns ( 82.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.230 ns" { JUDGE:JUDGE|TEMP[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.230 ns" { JUDGE:JUDGE|TEMP[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 1.847ns } { 0.000ns 0.383ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "4.691 ns - Smallest register memory " "Info: - Smallest register to memory requirement is 4.691 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination SYS_CLK 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"SYS_CLK\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source SYS_CLK 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"SYS_CLK\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.860 ns + Smallest " "Info: + Smallest clock skew is 4.860 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK destination 7.601 ns + Longest memory " "Info: + Longest clock path from clock \"SYS_CLK\" to destination memory is 7.601 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_93 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 25; CLK Node = 'SYS_CLK'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SYS_CLK } "NODE_NAME" } } { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 144 -280 -112 160 "SYS_CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.561 ns) + CELL(0.935 ns) 2.965 ns JUDGE:JUDGE\|FM_CORT\[0\] 2 REG LC_X11_Y6_N7 50 " "Info: 2: + IC(0.561 ns) + CELL(0.935 ns) = 2.965 ns; Loc. = LC_X11_Y6_N7; Fanout = 50; REG Node = 'JUDGE:JUDGE\|FM_CORT\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.496 ns" { SYS_CLK JUDGE:JUDGE|FM_CORT[0] } "NODE_NAME" } } { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.914 ns) + CELL(0.722 ns) 7.601 ns FM:ROM\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|ram_block1a7~porta_address_reg0 3 MEM M4K_X13_Y8 18 " "Info: 3: + IC(3.914 ns) + CELL(0.722 ns) = 7.601 ns; Loc. = M4K_X13_Y8; Fanout = 18; MEM Node = 'FM:ROM\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\|ram_block1a7~porta_address_reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.636 ns" { JUDGE:JUDGE|FM_CORT[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_jm21.tdf" "" { Text "E:/my project/quartusII/AD9851/db/altsyncram_jm21.tdf" 183 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.126 ns ( 41.13 % ) " "Info: Total cell delay = 3.126 ns ( 41.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.475 ns ( 58.87 % ) " "Info: Total interconnect delay = 4.475 ns ( 58.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.601 ns" { SYS_CLK JUDGE:JUDGE|FM_CORT[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.601 ns" { SYS_CLK SYS_CLK~out0 JUDGE:JUDGE|FM_CORT[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.561ns 3.914ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK source 2.741 ns - Shortest register " "Info: - Shortest clock path from clock \"SYS_CLK\" to source register is 2.741 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_93 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 25; CLK Node = 'SYS_CLK'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SYS_CLK } "NODE_NAME" } } { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 144 -280 -112 160 "SYS_CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.561 ns) + CELL(0.711 ns) 2.741 ns JUDGE:JUDGE\|TEMP\[0\] 2 REG LC_X11_Y6_N9 3 " "Info: 2: + IC(0.561 ns) + CELL(0.711 ns) = 2.741 ns; Loc. = LC_X11_Y6_N9; Fanout = 3; REG Node = 'JUDGE:JUDGE\|TEMP\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.272 ns" { SYS_CLK JUDGE:JUDGE|TEMP[0] } "NODE_NAME" } } { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.53 % ) " "Info: Total cell delay = 2.180 ns ( 79.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.561 ns ( 20.47 % ) " "Info: Total interconnect delay = 0.561 ns ( 20.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.741 ns" { SYS_CLK JUDGE:JUDGE|TEMP[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.741 ns" { SYS_CLK SYS_CLK~out0 JUDGE:JUDGE|TEMP[0] } { 0.000ns 0.000ns 0.561ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.601 ns" { SYS_CLK JUDGE:JUDGE|FM_CORT[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.601 ns" { SYS_CLK SYS_CLK~out0 JUDGE:JUDGE|FM_CORT[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.561ns 3.914ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.741 ns" { SYS_CLK JUDGE:JUDGE|TEMP[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.741 ns" { SYS_CLK SYS_CLK~out0 JUDGE:JUDGE|TEMP[0] } { 0.000ns 0.000ns 0.561ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.055 ns + " "Info: + Micro hold delay of destination is 0.055 ns" { } { { "db/altsyncram_jm21.tdf" "" { Text "E:/my project/quartusII/AD9851/db/altsyncram_jm21.tdf" 183 2 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.601 ns" { SYS_CLK JUDGE:JUDGE|FM_CORT[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.601 ns" { SYS_CLK SYS_CLK~out0 JUDGE:JUDGE|FM_CORT[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.561ns 3.914ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.741 ns" { SYS_CLK JUDGE:JUDGE|TEMP[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.741 ns" { SYS_CLK SYS_CLK~out0 JUDGE:JUDGE|TEMP[0] } { 0.000ns 0.000ns 0.561ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.230 ns" { JUDGE:JUDGE|TEMP[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.230 ns" { JUDGE:JUDGE|TEMP[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 1.847ns } { 0.000ns 0.383ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.601 ns" { SYS_CLK JUDGE:JUDGE|FM_CORT[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.601 ns" { SYS_CLK SYS_CLK~out0 JUDGE:JUDGE|FM_CORT[0] FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 0.561ns 3.914ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.741 ns" { SYS_CLK JUDGE:JUDGE|TEMP[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.741 ns" { SYS_CLK SYS_CLK~out0 JUDGE:JUDGE|TEMP[0] } { 0.000ns 0.000ns 0.561ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "SYS_CLK 16 " "Warning: Can't achieve minimum setup and hold requirement SYS_CLK along 16 path(s). See Report window for details." { } { } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}
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