ad9851.tan.qmsg

用VHDL语言编写的DDS正弦函数发生器

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "MCU_CLK " "Info: Assuming node \"MCU_CLK\" is an undefined clock" {  } { { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 256 -280 -112 272 "MCU_CLK" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "MCU_CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "JUDGE:JUDGE\|FM_CORT\[0\] " "Info: Detected ripple clock \"JUDGE:JUDGE\|FM_CORT\[0\]\" as buffer" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "JUDGE:JUDGE\|FM_CORT\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "SYS_CLK register AD9851:inst2\|STAT\[1\] register AD9851:inst2\|DAT_OUT\[0\] 14.578 ns " "Info: Slack time is 14.578 ns for clock \"SYS_CLK\" between source register \"AD9851:inst2\|STAT\[1\]\" and destination register \"AD9851:inst2\|DAT_OUT\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "184.43 MHz 5.422 ns " "Info: Fmax is 184.43 MHz (period= 5.422 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.780 ns + Largest register register " "Info: + Largest register to register requirement is 19.780 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination SYS_CLK 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"SYS_CLK\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source SYS_CLK 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"SYS_CLK\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.041 ns + Largest " "Info: + Largest clock skew is 0.041 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK destination 2.784 ns + Shortest register " "Info: + Shortest clock path from clock \"SYS_CLK\" to destination register is 2.784 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_93 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 25; CLK Node = 'SYS_CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SYS_CLK } "NODE_NAME" } } { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 144 -280 -112 160 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.604 ns) + CELL(0.711 ns) 2.784 ns AD9851:inst2\|DAT_OUT\[0\] 2 REG LC_X15_Y7_N6 1 " "Info: 2: + IC(0.604 ns) + CELL(0.711 ns) = 2.784 ns; Loc. = LC_X15_Y7_N6; Fanout = 1; REG Node = 'AD9851:inst2\|DAT_OUT\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.315 ns" { SYS_CLK AD9851:inst2|DAT_OUT[0] } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.30 % ) " "Info: Total cell delay = 2.180 ns ( 78.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.604 ns ( 21.70 % ) " "Info: Total interconnect delay = 0.604 ns ( 21.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.784 ns" { SYS_CLK AD9851:inst2|DAT_OUT[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.784 ns" { SYS_CLK SYS_CLK~out0 AD9851:inst2|DAT_OUT[0] } { 0.000ns 0.000ns 0.604ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK source 2.743 ns - Longest register " "Info: - Longest clock path from clock \"SYS_CLK\" to source register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_93 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 25; CLK Node = 'SYS_CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SYS_CLK } "NODE_NAME" } } { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 144 -280 -112 160 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns AD9851:inst2\|STAT\[1\] 2 REG LC_X15_Y5_N0 26 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X15_Y5_N0; Fanout = 26; REG Node = 'AD9851:inst2\|STAT\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.274 ns" { SYS_CLK AD9851:inst2|STAT[1] } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { SYS_CLK AD9851:inst2|STAT[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { SYS_CLK SYS_CLK~out0 AD9851:inst2|STAT[1] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.784 ns" { SYS_CLK AD9851:inst2|DAT_OUT[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.784 ns" { SYS_CLK SYS_CLK~out0 AD9851:inst2|DAT_OUT[0] } { 0.000ns 0.000ns 0.604ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { SYS_CLK AD9851:inst2|STAT[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { SYS_CLK SYS_CLK~out0 AD9851:inst2|STAT[1] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 58 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 58 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.784 ns" { SYS_CLK AD9851:inst2|DAT_OUT[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.784 ns" { SYS_CLK SYS_CLK~out0 AD9851:inst2|DAT_OUT[0] } { 0.000ns 0.000ns 0.604ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { SYS_CLK AD9851:inst2|STAT[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { SYS_CLK SYS_CLK~out0 AD9851:inst2|STAT[1] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.202 ns - Longest register register " "Info: - Longest register to register delay is 5.202 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AD9851:inst2\|STAT\[1\] 1 REG LC_X15_Y5_N0 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y5_N0; Fanout = 26; REG Node = 'AD9851:inst2\|STAT\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AD9851:inst2|STAT[1] } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.519 ns) + CELL(0.442 ns) 0.961 ns AD9851:inst2\|DAT_OUT\[7\]~753 2 COMB LC_X15_Y5_N4 1 " "Info: 2: + IC(0.519 ns) + CELL(0.442 ns) = 0.961 ns; Loc. = LC_X15_Y5_N4; Fanout = 1; COMB Node = 'AD9851:inst2\|DAT_OUT\[7\]~753'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.961 ns" { AD9851:inst2|STAT[1] AD9851:inst2|DAT_OUT[7]~753 } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.737 ns) + CELL(0.292 ns) 2.990 ns AD9851:inst2\|DAT_OUT\[7\]~775 3 COMB LC_X12_Y7_N7 8 " "Info: 3: + IC(1.737 ns) + CELL(0.292 ns) = 2.990 ns; Loc. = LC_X12_Y7_N7; Fanout = 8; COMB Node = 'AD9851:inst2\|DAT_OUT\[7\]~775'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.029 ns" { AD9851:inst2|DAT_OUT[7]~753 AD9851:inst2|DAT_OUT[7]~775 } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.345 ns) + CELL(0.867 ns) 5.202 ns AD9851:inst2\|DAT_OUT\[0\] 4 REG LC_X15_Y7_N6 1 " "Info: 4: + IC(1.345 ns) + CELL(0.867 ns) = 5.202 ns; Loc. = LC_X15_Y7_N6; Fanout = 1; REG Node = 'AD9851:inst2\|DAT_OUT\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.212 ns" { AD9851:inst2|DAT_OUT[7]~775 AD9851:inst2|DAT_OUT[0] } "NODE_NAME" } } { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.601 ns ( 30.78 % ) " "Info: Total cell delay = 1.601 ns ( 30.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.601 ns ( 69.22 % ) " "Info: Total interconnect delay = 3.601 ns ( 69.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.202 ns" { AD9851:inst2|STAT[1] AD9851:inst2|DAT_OUT[7]~753 AD9851:inst2|DAT_OUT[7]~775 AD9851:inst2|DAT_OUT[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.202 ns" { AD9851:inst2|STAT[1] AD9851:inst2|DAT_OUT[7]~753 AD9851:inst2|DAT_OUT[7]~775 AD9851:inst2|DAT_OUT[0] } { 0.000ns 0.519ns 1.737ns 1.345ns } { 0.000ns 0.442ns 0.292ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.784 ns" { SYS_CLK AD9851:inst2|DAT_OUT[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.784 ns" { SYS_CLK SYS_CLK~out0 AD9851:inst2|DAT_OUT[0] } { 0.000ns 0.000ns 0.604ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { SYS_CLK AD9851:inst2|STAT[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { SYS_CLK SYS_CLK~out0 AD9851:inst2|STAT[1] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.202 ns" { AD9851:inst2|STAT[1] AD9851:inst2|DAT_OUT[7]~753 AD9851:inst2|DAT_OUT[7]~775 AD9851:inst2|DAT_OUT[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.202 ns" { AD9851:inst2|STAT[1] AD9851:inst2|DAT_OUT[7]~753 AD9851:inst2|DAT_OUT[7]~775 AD9851:inst2|DAT_OUT[0] } { 0.000ns 0.519ns 1.737ns 1.345ns } { 0.000ns 0.442ns 0.292ns 0.867ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}