ad9851.map.qmsg

用VHDL语言编写的DDS正弦函数发生器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 27 17:05:59 2007 " "Info: Processing started: Fri Jul 27 17:05:59 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AD9851 -c AD9851 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AD9851 -c AD9851" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AD9851.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file AD9851.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AD9851-ONE " "Info: Found design unit 1: AD9851-ONE" {  } { { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 AD9851 " "Info: Found entity 1: AD9851" {  } { { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TLC5510.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TLC5510.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TLC5510-ONE " "Info: Found design unit 1: TLC5510-ONE" {  } { { "TLC5510.vhd" "" { Text "E:/my project/quartusII/AD9851/TLC5510.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 TLC5510 " "Info: Found entity 1: TLC5510" {  } { { "TLC5510.vhd" "" { Text "E:/my project/quartusII/AD9851/TLC5510.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SYS_TOP.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file SYS_TOP.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 SYS_TOP " "Info: Found entity 1: SYS_TOP" {  } { { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "JUDGE.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file JUDGE.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 JUDGE-ONE " "Info: Found design unit 1: JUDGE-ONE" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 JUDGE " "Info: Found entity 1: JUDGE" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SYS_TOP " "Info: Elaborating entity \"SYS_TOP\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TLC5510 TLC5510:inst " "Info: Elaborating entity \"TLC5510\" for hierarchy \"TLC5510:inst\"" {  } { { "SYS_TOP.bdf" "inst" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 16 72 264 112 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AD9851 AD9851:inst2 " "Info: Elaborating entity \"AD9851\" for hierarchy \"AD9851:inst2\"" {  } { { "SYS_TOP.bdf" "inst2" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 120 704 912 312 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "FM_EN AD9851.vhd(21) " "Warning (10492): VHDL Process Statement warning at AD9851.vhd(21): signal \"FM_EN\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "FM_DATA AD9851.vhd(24) " "Warning (10492): VHDL Process Statement warning at AD9851.vhd(24): signal \"FM_DATA\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JUDGE JUDGE:JUDGE " "Info: Elaborating entity \"JUDGE\" for hierarchy \"JUDGE:JUDGE\"" {  } { { "SYS_TOP.bdf" "JUDGE" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 48 304 496 144 "JUDGE" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "FM.vhd 2 1 " "Warning: Using design file FM.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fm-SYN " "Info: Found design unit 1: fm-SYN" {  } { { "FM.vhd" "" { Text "E:/my project/quartusII/AD9851/FM.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 FM " "Info: Found entity 1: FM" {  } { { "FM.vhd" "" { Text "E:/my project/quartusII/AD9851/FM.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FM FM:ROM " "Info: Elaborating entity \"FM\" for hierarchy \"FM:ROM\"" {  } { { "SYS_TOP.bdf" "ROM" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 48 520 680 128 "ROM" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram FM:ROM\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"FM:ROM\|altsyncram:altsyncram_component\"" {  } { { "FM.vhd" "altsyncram_component" { Text "E:/my project/quartusII/AD9851/FM.vhd" 80 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "FM:ROM\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"FM:ROM\|altsyncram:altsyncram_component\"" {  } { { "FM.vhd" "" { Text "E:/my project/quartusII/AD9851/FM.vhd" 80 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_jm21.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_jm21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_jm21 " "Info: Found entity 1: altsyncram_jm21" {  } { { "db/altsyncram_jm21.tdf" "" { Text "E:/my project/quartusII/AD9851/db/altsyncram_jm21.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_jm21 FM:ROM\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated " "Info: Elaborating entity \"altsyncram_jm21\" for hierarchy \"FM:ROM\|altsyncram:altsyncram_component\|altsyncram_jm21:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "JUDGE:JUDGE\|FM_CORT\[2\] data_in GND " "Warning: Reduced register \"JUDGE:JUDGE\|FM_CORT\[2\]\" with stuck data_in port to stuck value GND" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "JUDGE:JUDGE\|DAT_OUT\[0\] JUDGE:JUDGE\|TEMP\[0\] " "Info: Duplicate register \"JUDGE:JUDGE\|DAT_OUT\[0\]\" merged to single register \"JUDGE:JUDGE\|TEMP\[0\]\"" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "JUDGE:JUDGE\|DAT_OUT\[1\] JUDGE:JUDGE\|TEMP\[1\] " "Info: Duplicate register \"JUDGE:JUDGE\|DAT_OUT\[1\]\" merged to single register \"JUDGE:JUDGE\|TEMP\[1\]\"" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "JUDGE:JUDGE\|DAT_OUT\[2\] JUDGE:JUDGE\|TEMP\[2\] " "Info: Duplicate register \"JUDGE:JUDGE\|DAT_OUT\[2\]\" merged to single register \"JUDGE:JUDGE\|TEMP\[2\]\"" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "JUDGE:JUDGE\|DAT_OUT\[3\] JUDGE:JUDGE\|TEMP\[3\] " "Info: Duplicate register \"JUDGE:JUDGE\|DAT_OUT\[3\]\" merged to single register \"JUDGE:JUDGE\|TEMP\[3\]\"" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "JUDGE:JUDGE\|DAT_OUT\[4\] JUDGE:JUDGE\|TEMP\[4\] " "Info: Duplicate register \"JUDGE:JUDGE\|DAT_OUT\[4\]\" merged to single register \"JUDGE:JUDGE\|TEMP\[4\]\"" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "JUDGE:JUDGE\|DAT_OUT\[5\] JUDGE:JUDGE\|TEMP\[5\] " "Info: Duplicate register \"JUDGE:JUDGE\|DAT_OUT\[5\]\" merged to single register \"JUDGE:JUDGE\|TEMP\[5\]\"" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "JUDGE:JUDGE\|DAT_OUT\[6\] JUDGE:JUDGE\|TEMP\[6\] " "Info: Duplicate register \"JUDGE:JUDGE\|DAT_OUT\[6\]\" merged to single register \"JUDGE:JUDGE\|TEMP\[6\]\"" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "JUDGE:JUDGE\|DAT_OUT\[7\] JUDGE:JUDGE\|TEMP\[7\] " "Info: Duplicate register \"JUDGE:JUDGE\|DAT_OUT\[7\]\" merged to single register \"JUDGE:JUDGE\|TEMP\[7\]\"" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "JUDGE:JUDGE\|FM_CORT\[1\] JUDGE:JUDGE\|FM_CORT\[0\] " "Info: Duplicate register \"JUDGE:JUDGE\|FM_CORT\[1\]\" merged to single register \"JUDGE:JUDGE\|FM_CORT\[0\]\", power-up level changed" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "JUDGE:JUDGE\|ROM_CLK JUDGE:JUDGE\|FM_CORT\[0\] " "Info: Duplicate register \"JUDGE:JUDGE\|ROM_CLK\" merged to single register \"JUDGE:JUDGE\|FM_CORT\[0\]\"" {  } { { "JUDGE.vhd" "" { Text "E:/my project/quartusII/AD9851/JUDGE.vhd" 8 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "TCL_OE GND " "Warning: Pin \"TCL_OE\" stuck at GND" {  } { { "SYS_TOP.bdf" "" { Schematic "E:/my project/quartusII/AD9851/SYS_TOP.bdf" { { 0 936 1112 16 "TCL_OE" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "AD9851.vhd" "" { Text "E:/my project/quartusII/AD9851/AD9851.vhd" 21 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "211 " "Info: Implemented 211 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "22 " "Info: Implemented 22 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "144 " "Info: Implemented 144 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "32 " "Info: Implemented 32 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 27 17:06:12 2007 " "Info: Processing ended: Fri Jul 27 17:06:12 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}