chose.vhd

来自「用VHDL语言编写的DDS正弦函数发生器」· VHDL 代码 · 共 84 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CHOSE IS
	PORT(SYS_CLK,CLK_440:IN STD_LOGIC;
		 FM_ON,MCU_CLK,FLAG:IN STD_LOGIC;
		 DAT_32:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
		 DAT_IN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		 CLK_OUT,FLAG_OUT:OUT STD_LOGIC;
		 DAT_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE ONE OF CHOSE IS
	SIGNAL STAT:STD_LOGIC_VECTOR(3 DOWNTO 0);
	BEGIN
	PROCESS(SYS_CLK)
		BEGIN
		IF SYS_CLK'EVENT AND SYS_CLK='1' THEN
		---------------------------------------------------------
			IF FM_ON='1' THEN--FM_ON='1'调频输出使能
				IF CLK_440='1' THEN
					STAT<="0000";
				--写数据-----------------------------------------
				ELSIF STAT="0000" THEN
					FLAG_OUT<='1';--写数据
					CLK_OUT<='0';
					DAT_OUT<=DAT_32(31 DOWNTO 24);--1
					STAT<="0001";
				ELSIF STAT="0001" THEN
					CLK_OUT<='1';
					STAT<="0010";
				ELSIF STAT="0010" THEN
					CLK_OUT<='0';
					DAT_OUT<=DAT_32(23 DOWNTO 16);--2
					STAT<="0011";
				ELSIF STAT="0011" THEN
					CLK_OUT<='1';
					STAT<="0100";
				ELSIF STAT="0100" THEN
					CLK_OUT<='0';
					DAT_OUT<=DAT_32(15 DOWNTO 8);--3
					STAT<="0101";
				ELSIF STAT="0101" THEN
					CLK_OUT<='1';
					STAT<="0110";
				ELSIF STAT="0110" THEN
					CLK_OUT<='0';
					DAT_OUT<=DAT_32(7 DOWNTO 0);--4
					STAT<="0111";
				ELSIF STAT="0111" THEN
					CLK_OUT<='1';
					STAT<="1000";
				--写命令-------------------------------------------
				ELSIF STAT="1000" THEN
					CLK_OUT<='0';
					FLAG_OUT<='0';--写命令
					DAT_OUT<="00000001";--系统数据发送初始化
					STAT<="1001";
				ELSIF STAT="1001" THEN
					CLK_OUT<='1';
					STAT<="1010";
				ELSIF STAT="1010" THEN
					CLK_OUT<='0';
					DAT_OUT<="00000010";--发送频率
					STAT<="1011";
				ELSIF STAT="1011" THEN
					CLK_OUT<='1';
					STAT<="1100";
				ELSIF STAT="1100" THEN
					CLK_OUT<='0';
					STAT<="1111";
				END IF;
			--------------------------------------------------------
			ELSIF FM_ON='0' THEN --FM_ON='0'关闭FM调频
				FLAG_OUT<=FLAG;
				CLK_OUT<=MCU_CLK;
				DAT_OUT<=DAT_IN;
			END IF;
		------------------------------------------------------------
		END IF;
	----------------------------------------------------------------
	END PROCESS;
END;