judge.vhd

用VHDL语言编写的DDS正弦函数发生器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JUDGE IS
	PORT(DAT_IN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		 SYS_CLK:IN STD_LOGIC;
		 DAT_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		 ROM_CLK:OUT STD_LOGIC;
		 FM_CORT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END;
ARCHITECTURE ONE OF JUDGE IS
	SIGNAL TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);
	BEGIN
	PROCESS(SYS_CLK)
		BEGIN
		IF SYS_CLK'EVENT AND SYS_CLK='1' THEN
			IF TEMP/=DAT_IN THEN
				ROM_CLK<='1';
				DAT_OUT<=DAT_IN;
				FM_CORT<="001";
				TEMP<=DAT_IN;
			ELSE
				ROM_CLK<='0';
				FM_CORT<="010";
			END IF;
		END IF;
	END PROCESS;
END;