d16_d32.vhd

用VHDL语言编写的DDS正弦函数发生器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY D16_D32 IS
	PORT(D16:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		 D32:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END;
ARCHITECTURE ONE OF D16_D32 IS
	BEGIN
	D32(31 DOWNTO 16)<="0000000000000000";
	D32(15 DOWNTO 0)<=D16;
END;