ad9851.map.rpt

用VHDL语言编写的DDS正弦函数发生器

; Source assignments for FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------+
; Assignment                      ; Value              ; From ; To                             ;
+---------------------------------+--------------------+------+--------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                              ;
+---------------------------------+--------------------+------+--------------------------------+


+-------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FM:ROM|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+------------------------------+
; Parameter Name                     ; Value           ; Type                         ;
+------------------------------------+-----------------+------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                      ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                   ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                 ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                 ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE               ;
; OPERATION_MODE                     ; ROM             ; Untyped                      ;
; WIDTH_A                            ; 32              ; Integer                      ;
; WIDTHAD_A                          ; 8               ; Integer                      ;
; NUMWORDS_A                         ; 256             ; Integer                      ;
; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                      ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                      ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                      ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                      ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                      ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                      ;
; WIDTH_B                            ; 1               ; Untyped                      ;
; WIDTHAD_B                          ; 1               ; Untyped                      ;
; NUMWORDS_B                         ; 1               ; Untyped                      ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                      ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                      ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                      ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                      ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                      ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                      ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                      ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                      ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                      ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                      ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                      ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                      ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                      ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                      ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                      ;
; BYTE_SIZE                          ; 8               ; Untyped                      ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                      ;
; INIT_FILE                          ; FM.MIF          ; Untyped                      ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                      ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                      ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                      ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                      ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                      ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                      ;
; DEVICE_FAMILY                      ; Cyclone         ; Untyped                      ;
; CBXI_PARAMETER                     ; altsyncram_jm21 ; Untyped                      ;
+------------------------------------+-----------------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Jul 27 17:05:59 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AD9851 -c AD9851
Info: Found 2 design units, including 1 entities, in source file AD9851.vhd
    Info: Found design unit 1: AD9851-ONE
    Info: Found entity 1: AD9851
Info: Found 2 design units, including 1 entities, in source file TLC5510.vhd
    Info: Found design unit 1: TLC5510-ONE
    Info: Found entity 1: TLC5510
Info: Found 1 design units, including 1 entities, in source file SYS_TOP.bdf
    Info: Found entity 1: SYS_TOP
Info: Found 2 design units, including 1 entities, in source file JUDGE.vhd
    Info: Found design unit 1: JUDGE-ONE
    Info: Found entity 1: JUDGE
Info: Elaborating entity "SYS_TOP" for the top level hierarchy
Info: Elaborating entity "TLC5510" for hierarchy "TLC5510:inst"
Info: Elaborating entity "AD9851" for hierarchy "AD9851:inst2"
Warning (10492): VHDL Process Statement warning at AD9851.vhd(21): signal "FM_EN" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at AD9851.vhd(24): signal "FM_DATA" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "JUDGE" for hierarchy "JUDGE:JUDGE"
Warning: Using design file FM.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: fm-SYN
    Info: Found entity 1: FM
Info: Elaborating entity "FM" for hierarchy "FM:ROM"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "FM:ROM|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "FM:ROM|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_jm21.tdf
    Info: Found entity 1: altsyncram_jm21
Info: Elaborating entity "altsyncram_jm21" for hierarchy "FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated"
Warning: Reduced register "JUDGE:JUDGE|FM_CORT[2]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "JUDGE:JUDGE|DAT_OUT[0]" merged to single register "JUDGE:JUDGE|TEMP[0]"
    Info: Duplicate register "JUDGE:JUDGE|DAT_OUT[1]" merged to single register "JUDGE:JUDGE|TEMP[1]"
    Info: Duplicate register "JUDGE:JUDGE|DAT_OUT[2]" merged to single register "JUDGE:JUDGE|TEMP[2]"
    Info: Duplicate register "JUDGE:JUDGE|DAT_OUT[3]" merged to single register "JUDGE:JUDGE|TEMP[3]"
    Info: Duplicate register "JUDGE:JUDGE|DAT_OUT[4]" merged to single register "JUDGE:JUDGE|TEMP[4]"
    Info: Duplicate register "JUDGE:JUDGE|DAT_OUT[5]" merged to single register "JUDGE:JUDGE|TEMP[5]"
    Info: Duplicate register "JUDGE:JUDGE|DAT_OUT[6]" merged to single register "JUDGE:JUDGE|TEMP[6]"
    Info: Duplicate register "JUDGE:JUDGE|DAT_OUT[7]" merged to single register "JUDGE:JUDGE|TEMP[7]"
    Info: Duplicate register "JUDGE:JUDGE|FM_CORT[1]" merged to single register "JUDGE:JUDGE|FM_CORT[0]", power-up level changed
    Info: Duplicate register "JUDGE:JUDGE|ROM_CLK" merged to single register "JUDGE:JUDGE|FM_CORT[0]"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "TCL_OE" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 211 device resources after synthesis - the final resource count might be different
    Info: Implemented 22 input pins
    Info: Implemented 13 output pins
    Info: Implemented 144 logic cells
    Info: Implemented 32 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Fri Jul 27 17:06:12 2007
    Info: Elapsed time: 00:00:14