uart.v

简化的串口通信

/******************************************************************************
*
*    File Name:  uart.v
*      Version:  1.1
*         Date:  January 22, 2000
*        Model:  Uart Chip
* Dependencies:  txmit.v, rcvr.v
*
*      Company:  Xilinx
*
*
*   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
*                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
*                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
*                Copyright (c) 2000 Xilinx, Inc.
*                All rights reserved
*
******************************************************************************/

`timescale 1ns / 100ps

module uart (dout,data_ready,framing_error,parity_error,rxd,clk32m,reset,rdn,tbre,tsre,sdo,led);

output tbre ;
output tsre ;
output sdo ;
//input [7:0] din ;
input reset ;
input clk32m ;
//input wrn ;
input rxd ;
input rdn ;
output [7:0] dout ;
output data_ready ;
output framing_error ;
output parity_error ;
output [7:0] led;

reg [7:0] din;
reg       wrn;
reg [7:0] counter;
reg [7:0] delay; 
wire      clk16x;

//rcvr u1 (dout,data_ready,framing_error,parity_error,rxd,clk16x,rst,rdn) ;

txmit TXD (din,tbre,tsre,rst,clk16x,wrn,sdo) ;

baud_clk BAUD(rst,clk32m,clk16x);

assign rst = !reset;

always @(posedge tsre)
if(rst)
   counter[7:0] = 8'h0;
else
   counter[7:0] = counter[7:0] + 1;

assign led[7:0] = counter[7:0];

always @(posedge clk16x or posedge rst)
if(rst)
    delay[7:0] = 0;
else if(tbre == 1)
   delay[7:0] = 0;
else 
   delay[7:0] = delay[7:0] + 1;

always @(posedge clk16x)
    if(2 <= delay[7:0])
        din = counter[7:0];

always @(posedge clk16x)
    if(rst)
        wrn = 0;
    else if(5<= delay[7:0] && delay[7:0] <= 10)
        wrn = 0;
    else
        wrn = 1;


endmodule