arm920t.s

来自「ADS下的bios工程」· S 代码 · 共 692 行 · 第 1/2 页

#include <bios/linkage.h>
#include <bios/s3c2410x.h>

#define R1_iA   (1<<31) /* Async. clock select */
#define R1_nF   (1<<30) /* not Fast Bus select */
#define R1_RR   (1<<14) /* Round robin replacement */
#define R1_V    (1<<13) /* Base location of exception vector*/
#define R1_I    (1<<12) /* Instruction Cache enable */
#define R1_R    (1<<9)  /* ROM protection */
#define R1_S    (1<<8)  /* System protection */
#define R1_B    (1<<7)  /* Endian Big/Little */
#define R1_C    (1<<2)  /* Data Cache enable */
#define R1_A    (1<<1)  /* Alignment fault enable */
#define R1_M    (1<<0)  /* MMU enable */

	.text

/*-----------------------------------------------
 * u32 IDCode(void)
 *-----------------------------------------------*/
	.macro IDCode
	mrc	p15, 0, r0, c0, c0, 0
	.endm

/*-----------------------------------------------
 * u32 CacheType(void)
 *-----------------------------------------------*/
	.macro CacheType
	mrc	p15, 0, r0, c0, c0, 1
	.endm

/*===================================================================
 * Cache, Clock mode, Protection, Endian ... control functions
 *===================================================================*/

/*-----------------------------------------------
 * void SetRegister1(u32 bits)
 *	r0 : R1_iA, R1_nF, R1_RR, R1_V, R1_I, 
 *	     R1_R, R1_S, R1_B, R1_C, R1_A, R1_M
 *-----------------------------------------------*/
	.macro SetRegister1
	mrc	p15, 0, r1, c1, c0, 0
	orr	r0, r1, r0
	mcr	p15, 0, r0, c1, c0, 0
	mov	r0, r0
	mov	r0, r0
	mov	r0, r0
	.endm

ENTRY(SetRegister1)
	SetRegister1
	mov	pc,lr

/*-----------------------------------------------
 * void ClearRegister1(u32 bits)
 *	r0 : R1_iA, R1_nF, R1_RR, R1_V, R1_I, 
 *	     R1_R, R1_S, R1_B, R1_C, R1_A, R1_M
 *-----------------------------------------------*/
	.macro ClearRegister1
	mrc	p15, 0, r1, c1, c0, 0
	bic	r0, r1, r0
	mcr	p15, 0, r0, c1, c0, 0
	.endm

ENTRY(ClearRegister1)
	ClearRegister1
	mov 	pc,lr

/*------------------------------------------------
 * void icache_enable(void)
 *-----------------------------------------------*/
	.macro icache_enable
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #R1_I
	mcr	p15, 0, r0, c1, c0, 0
	.endm

/*------------------------------------------------
 * ICache Enable Function
 *-----------------------------------------------*/
ENTRY(icache_enable)
        icache_enable
        mov     pc, lr

/*------------------------------------------------
 * void icache_disable(void)
 *-----------------------------------------------*/
	.macro icache_disable
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #R1_I
	mcr	p15, 0, r0, c1, c0, 0
	.endm

/*------------------------------------------------
 * ICache Disable Function
 *-----------------------------------------------*/
ENTRY(icache_disable)
        icache_disable
        mov     pc, lr

/*------------------------------------------------
 * void dcache_enable(void)
 *-----------------------------------------------*/
	.macro dcache_enable
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #R1_C
	mcr	p15, 0, r0, c1, c0, 0
	.endm

/*------------------------------------------------
 * DCache Enable Function
 *-----------------------------------------------*/
ENTRY(dcache_enable)
        dcache_enable
        mov     pc, lr

/*------------------------------------------------
 * void dcache_disable(void)
 *-----------------------------------------------*/
	.macro dcache_disable
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #R1_C
	mcr	p15, 0, r0, c1, c0, 0
	.endm

/*------------------------------------------------
 * DCache Disable Function
 *-----------------------------------------------*/
ENTRY(dcache_disable)
        dcache_disable
        mov     pc, lr

/*------------------------------------------------
 * void align_fault_enable(void)
 *-----------------------------------------------*/
	.macro align_fault_enable
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #R1_A
	mcr	p15, 0, r0, c1, c0, 0
	.endm

ENTRY(align_fault_enable)
	align_fault_enable
	mov	pc,lr

/*------------------------------------------------
 * void align_fault_disable(void)
 *-----------------------------------------------*/
	.macro align_fault_disable
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #R1_A
	mcr	p15, 0, r0, c1, c0, 0
	.endm

ENTRY(align_fault_disable)
	align_fault_disable
	mov 	pc,lr

/*------------------------------------------------
 * void mmu_enable(void)
 *-----------------------------------------------*/
	.macro mmu_enable
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #R1_M
	mcr	p15, 0, r0, c1, c0, 0
	.endm

/*------------------------------------------------
 * MMU Enable Function
 *-----------------------------------------------*/
ENTRY(mmu_enable)
        mmu_enable
        mov     pc, lr

/*------------------------------------------------
 * void mmu_disable(void)
 *-----------------------------------------------*/
	.macro mmu_disable
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #R1_M
	mcr	p15, 0, r0, c1, c0, 0
	.endm
/*------------------------------------------------
 * MMU Diable Function
 *-----------------------------------------------*/
ENTRY(mmu_disable)
	mmu_disable
	mov	pc,lr

/*------------------------------------------------
 * void fast_bus_mode(void)
 * FCLK:HCLK= 1:1
 *-----------------------------------------------*/
	.macro fast_bus_mode
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #R1_iA | R1_nF
	mcr	p15, 0, r0, c1, c0, 0
	.endm

ENTRY(fast_bus_mode)
	fast_bus_mode
	mov	pc,lr

/*------------------------------------------------
 * void async_bus_mode(void)
 * FCLK:HCLK= 1:2
 *-----------------------------------------------*/
	.macro async_bus_mode
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #R1_nF | R1_iA
	mcr	p15, 0, r0, c1, c0, 0
	.endm

ENTRY(async_bus_mode)
	async_bus_mode
	mov	pc,lr


/*===================================================================
 * Register2 : Translation table base register
 *===================================================================*/

/*------------------------------------------------
 * void SetRegister2(u32 base)
 *	base : TTBase(bit[13:0] should be zero)
 *-----------------------------------------------*/
	.macro SetRegister2
	mcr	p15, 0, r0, c2, c0, 0
	.endm

/*------------------------------------------------
 * SetRegister2(u32 base) function
 *-----------------------------------------------*/
ENTRY(SetRegister2)
	SetRegister2
	mov 	pc,lr

/*------------------------------------------------
 * u32 ReadRegister2(void)
 *	return : TTBase(bit[13:0] are unpredictable)
 *-----------------------------------------------*/
	.macro ReadRegister2
	mrc	p15, 0, r0, c2, c0, 0
	.endm

/*------------------------------------------------
 * ReadRegister2(u32 base) function
 *-----------------------------------------------*/
ENTRY(ReadRegister2)
        ReadRegister2
        mov     pc,lr


/*===================================================================
 * Register3 : Domain access control register
 *===================================================================*/

/*------------------------------------------------
 * void MMU_SetDomain(u32 domain)
 *	domain : 16 domain(each of 2-bit field)
 *	0 0 --> No Access(Generate a domain fault)
 *	0 1 --> Client(Checked in the section or page descriptor)
 *	1 0 --> Reserved
 *	1 1 --> Manager(Not checked)
 *-----------------------------------------------*/
	.macro SetRegister3
	mcr	p15, 0, r0, c3, c0, 0
	.endm

/*------------------------------------------------
 * SetRegister3(void) Function
 *-----------------------------------------------*/
ENTRY(SetRegister3)
        SetRegister3
        mov     pc,lr

/*------------------------------------------------
 * u32 ReadRegister3(void)
 *	return : 16 domain(each of 2-bit field)
 *-----------------------------------------------*/
	.macro ReadRegister3
	mrc	p15, 0, r0, c3, c0, 0
	.endm

/*------------------------------------------------
 * ReadRegister3(void) Function
 *-----------------------------------------------*/
ENTRY(ReadRegister3)
	ReadRegister3
	mov 	pc,lr


/*===================================================================
 * Register7 : Cache operations register(Write-only)
 *===================================================================*/

/*------------------------------------------------
 * void InvalidateIDCache(void)
 *	r0 : SBZ(should be zero)
 *-----------------------------------------------*/
	.macro InvalidateIDCache
	mcr	p15, 0, r0, c7, c7, 0
	.endm

ENTRY(InvalidateIDCache)
	InvalidateIDCache
	mov	pc,lr

/*------------------------------------------------
 * void InvalidateICache(void)
 *	r0 : SBZ(should be zero)
 *-----------------------------------------------*/
	.macro InvalidateICache
	mcr	p15, 0, r0, c7, c5, 0
	.endm

/*------------------------------------------------
 * InvalidateICache Function
 *-----------------------------------------------*/
ENTRY(InvalidateICache)
        InvalidateICache
        mov     pc,lr

/*------------------------------------------------
 * void InvalidateICacheMVA(u32 mva)
 *	mva : MVA[31:5], SBZ[4:0]
 *-----------------------------------------------*/
	.macro InvalidateICacheMVA
	mcr	p15, 0, r0, c7, c5, 1
	.endm
	
ENTRY(InvalidateICacheMVA)
	InvalidateICacheMVA
	mov	pc,lr

/*------------------------------------------------
 * void PrefetchICacheMVA(u32 mva)
 *	mva : MVA[31:5], SBZ[4:0]
 *-----------------------------------------------*/
	.macro PrefetchICacheMVA
	mcr	p15, 0, r0, c7, c13, 1
	.endm

ENTRY(PrefetchICacheMVA)
	PrefetchICacheMVA
	mov	pc,lr