arm920t.s

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/*------------------------------------------------
 * void InvalidateDCache(void)
 *	r0 : SBZ(should be zero)
 *-----------------------------------------------*/
	.macro InvalidateDCache
	mcr	p15, 0, r0, c7, c6, 0
	.endm

ENTRY(InvalidateDCache)
	InvalidateDCache
	mov	pc,lr

/*------------------------------------------------
 * void InvalidateDCacheMVA(u32 mva)
 *	mva : MVA[31:5], SBZ[4:0]
 *-----------------------------------------------*/
	.macro InvalidateDCacheMVA
	mcr	p15, 0, r0, c7, c6, 1
	.endm

ENTRY(InvalidateDCacheMVA)
	InvalidateDCacheMVA
	mov	pc,lr


/*------------------------------------------------
 * void CleanDCacheMVA(u32 mva)
 *	mva : MVA[31:5], SBZ[4:0]
 *-----------------------------------------------*/
	.macro CleanDCacheMVA
	mcr	p15, 0, r0, c7, c10, 1
	.endm

ENTRY(CleanDCacheMVA)
	CleanDCacheMVA
	mov	pc,lr

/*------------------------------------------------
 * void CleanInvalidateDCacheMVA(u32 mva)
 *	mva : MVA[31:5], SBZ[4:0]
 *-----------------------------------------------*/
	.macro CleanInvalidateDCacheMVA
	mcr	p15, 0, r0, c7, c14, 1
	.endm

ENTRY(CleanInvalidateDCacheMVA)
	CleanInvalidateDCacheMVA
	mov	pc,lr

/*------------------------------------------------
 * void CleanDCacheIndex(u32 index)
 *	index :
 *-----------------------------------------------*/
	.macro CleanDCacheIndex
	mcr	p15, 0, r0, c7, c10, 2
	.endm

ENTRY(CleanDCacheIndex)
	CleanDCacheIndex
	mov	pc,lr

/*------------------------------------------------
 * void CleanInvalidateDCacheIndex(u32 index)
 *	index :
 *-----------------------------------------------*/
	.macro CleanInvalidateDCacheIndex
	mcr	p15, 0, r0, c7, c14, 2
	.endm

/*------------------------------------------------
 *  CleanInvalidateDCacheIndex(u32 index) Function
 *-----------------------------------------------*/
ENTRY(CleanInvalidateDCacheIndex)
	CleanInvalidateDCacheIndex
	mov	pc,lr

/*------------------------------------------------
 * void DrainWriteBuffer(void)
 *	r0 : SBZ(should be zero)
 *-----------------------------------------------*/
	.macro DrainWriteBuffer
	mcr	p15, 0, r0, c7, c0, 4
	.endm

ENTRY(DrainWriteBuffer)
	DrainWriteBuffer
	mov	pc,lr

/*------------------------------------------------
 * void WaitForInterrupt(void)
 *	r0 : SBZ(should be zero)
 *-----------------------------------------------*/
	.macro WaitForInterrupt
	mcr	p15, 0, r0, c7, c0, 4
	.endm

ENTRY(WaitForInterrupt)
	WaitForInterrupt
	mov	pc,lr


/*===================================================================
 * Register8 : Translation lookaside buffer(TLB) operations register
 *	(Write-only)
 *===================================================================*/

/*------------------------------------------------
 * void InvalidateTLB(void)
 *-----------------------------------------------*/
	.macro InvalidateTLB
	mcr	p15, 0, r0, c8, c7, 0
	.endm

/*------------------------------------------------
 * InvalidateTLB Funtion
 *-----------------------------------------------*/
ENTRY(InvalidateTLB)
	InvalidateTLB
	mov	pc,lr


/*------------------------------------------------
 * void InvalidateITLB(void)
 *-----------------------------------------------*/
	.macro InvalidateITLB
	mcr	p15, 0, r0, c8, c5, 0
	.endm

ENTRY(InvalidateITLB)
	InvalidateITLB
	mov	pc,lr

/*------------------------------------------------
 * void InvalidateITLBMVA(u32 mva)
 *	mva : MVA[31:10], SBZ[9:0]
 *-----------------------------------------------*/
	.macro InvalidateITLBMVA
	mcr	p15, 0, r0, c8, c5, 1
	.endm

ENTRY(InvalidateITLBMVA)
	InvalidateITLBMVA
	mov	pc,lr

/*------------------------------------------------
 * void InvalidateDTLB(void)
 *-----------------------------------------------*/
	.macro InvalidateDTLB
	mcr	p15, 0, r0, c8, c6, 0
	.endm

ENTRY(InvalidateDTLB)
	InvalidateDTLB
	mov	pc,lr

/*------------------------------------------------
 * void InvalidateDTLBMVA(u32 mva)
 *	mva : MVA[31:10], SBZ[9:0]
 *-----------------------------------------------*/
	.macro InvalidateDTLBMVA
	mcr	p15, 0, r0, c8, c6, 1
	.endm

ENTRY(InvalidateDTLBMVA)
	InvalidateDTLBMVA
	mov	pc,lr


/*===================================================================
 * Register9 : Cache lock down register
 *===================================================================*/

/*------------------------------------------------
 * void SetDCacheLockdownBase(u32 base)
 *	base : victim & lockdown base
 *-----------------------------------------------*/
	.macro SetDCacheLockdownBase
	mcr	p15, 0, r0, c9, c0, 0
	.endm
	
ENTRY(SetDCacheLockdownBase)
	SetDCacheLockdownBase
	mov	pc,lr

/*------------------------------------------------
 * void SetICacheLockdownBase(u32 base)
 *	base : victim & lockdown base
 *-----------------------------------------------*/
	.macro SetICacheLockdownBase
	mcr	p15, 0, r0, c9, c0, 1
	.endm

ENTRY(SetICacheLockdownBase)
	SetICacheLockdownBase
	mov	pc,lr


/*===================================================================
 * Register10 : TLB lock down register
 *===================================================================*/

/*------------------------------------------------
 * void SetDTLBLockdown(u32 baseVictim)
 *	baseVictim :
 *-----------------------------------------------*/
	.macro SetDTLBLockdown
	mcr	p15, 0, r0, c10, c0, 0
	.endm
	
ENTRY(SetDTLBLockdown)
	SetDTLBLockdown
	mov	pc,lr

/*-----------------------------------------------
 * void SetITLBLockdown(u32 baseVictim)
 *	baseVictim :
 *-----------------------------------------------*/
	.macro SetITLBLockdown
	mcr	p15, 0, r0, c10, c0, 1
	.endm

ENTRY(SetITLBLockdown)
	SetITLBLockdown
	mov	pc,lr

/*===================================================================
 * Register13 : process identifier register
 *===================================================================*/
/*------------------------------------
 * void SetProcessId(u32 pid)
 *	pid : Proc ID[31:25], SBZ[24:0]
 *-----------------------------------*/
	.macro SetProcessId
	mcr	p15, 0, r0, c13, c0, 0
	.endm

ENTRY(SetProcessId)
	SetProcessId
	mov	pc,lr

ENTRY(MMU_Init)
	mov	r11, lr
	mov	r0, #R1_C
	orr	r0, r0, #R1_I
	ClearRegister1

	mov	r1, #0		/* ways */
02:	mov	r2, #0		/* line */
	mov	r3, r1, lsl #26
01:	orr	r0, r3, r2, lsl #5
	add	r2, r2, #1
	CleanInvalidateDCacheIndex
	cmp	r2, #7
	ble	01b
	add	r1, r1, #1
	cmp	r1, #63
	ble	02b

	mov	r0, #0x0
	InvalidateICache
	mov	r0, #R1_M
	ClearRegister1
	InvalidateTLB
	/* table created(r0:MMU_Base, r1:paddr, r2:vaddr, r3:size, r4:attr) */
	/* entry = MMU_Base + (vaddr >> 18) */
	/* value = (((paddr >> 20) + 1M) << 20) | attr */
	bl	MMUTT_Init

	ldr     r0, =MMUTT_STARTADDRESS
	SetRegister2			@ Set Translation Table Base
	ldr	r0, =0x5555555F
	SetRegister3
	mov	r0, #0x0
	SetProcessId
	mov	r0, #R1_A | R1_C | R1_M
	orr	r0, r0, #R1_I
	
	SetRegister1			@ MMU Enable
	mov	pc, r11

ENTRY(MMUTT_Init)
	mov	r12, lr
	ldr	r0, =MMUTT_STARTADDRESS		@ Table Base Address
	mov	r6, #0x9
	ldr	r5, =.ROM0_TT_Value
01:	ldmia	r5!, {r1-r4}
	bl	MMU_Memory_Bank_Init
	subs	r6, r6, #1
	bne	01b
	mov	pc, r12
/*-----------------------------
 * r1 : Physical Address
 * r2 : Virtual Address
 * r3 : Setting Count by MB
 * r4 : Attr
 *----------------------------*/
ENTRY(MMU_Memory_Bank_Init)
	add	r2, r0, r2, lsr #18
	add	r1, r1, r4
	str	r1, [r2], #4
06:	add	r1, r1, #1 << 20
	str	r1, [r2], #4
	subs	r3, r3, #1
	bne	06b
	mov	pc, lr

.ROM0_TT_Value:
	.long	0x00000000	@ Physical Address (nGCS0)
	.long	0x00000000	@ Virtual Address
	.long	0x7F		@ MMU Table Entry Count(by MB)
	.long	0x00000C1A	@ 128 MB(Base:0x00000000, Cache ON, Buffer OFF)
	.long	0x08000000	@ Physical Address (nGCS1)
	.long	0x08000000	@ Virtual Address
	.long	0x7F		@ MMU Table Entry Count(by MB)
	.long	0x00000C1A	@ 128 MB(Base:0x00000000, Cache ON, Buffer OFF)
	.long	0x10000000	@ Physical Address (nGCS2)
	.long	0x10000000	@ Virtual Address
	.long	0x7F		@ MMU Table Entry Count(by MB)
	.long	0x00000C12	@ 128 MB(Base:0x00000000, Cache OFF, Buffer OFF)
	.long	0x18000000	@ Physical Address (nGCS3)
	.long	0x18000000	@ Virtual Address
	.long	0x7F		@ MMU Table Entry Count(by MB)
	.long	0x00000C12	@ 128 MB(Base:0x00000000, Cache OFF, Buffer OFF)
	.long	0x20000000	@ Physical Address (nGCS4)
	.long	0x20000000	@ Virtual Address
	.long	0x7F		@ MMU Table Entry Count(by MB)
	.long	0x00000C12	@ 128 MB(Base:0x00000000, Cache OFF, Buffer OFF)
	.long	0x28000000	@ Physical Address (nGCS5)
	.long	0x28000000	@ Virtual Address
	.long	0x7F		@ MMU Table Entry Count(by MB)
	.long	0x00000C12	@ 128 MB(Base:0x00000000, Cache OFF, Buffer OFF)
	.long	0x30000000	@ Physical Address (nGCS6)
	.long	0x30000000	@ Virtual Address
	.long	0x7F		@ MMU Table Entry Count(by MB)
	.long	0x00000C1E	@ 128 MB(Base:0x00000000, Cache ON, Buffer ON)
	.long	0x38000000	@ Physical Address (nGCS7)
	.long	0x38000000	@ Virtual Address
	.long	0x7F		@ MMU Table Entry Count(by MB)
	.long	0x00000C1E	@ 128 MB(Base:0x00000000, Cache ON, Buffer ON)
	.long	0x48000000	@ Physical Address (SFR)
	.long	0x48000000	@ Virtual Address
	.long	0xFF		@ MMU Table Entry Count(by MB)
	.long	0x00000C12	@ 256 MB(Base:0x00000000, Cache OFF, Buffer OFF)