dig_clk_lcd.txt

This a vhdl programme for realise an electron watch by max-plus II. The function includes time showi

dig_clk_lcd 
=======================================================================================
bskz.vhdl
----------------------------------
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;



entity bskz is

  port(mshi,mge,sshi,sge:in std_logic_vector(3 downto 0);

       clk:in std_logic;

	  cp500: buffer std_logic:='1';

	  cp1000:buffer std_logic:='1'); 

end bskz;



architecture Behavioral of bskz is



begin

   process(clk)

   begin

      if clk'event and clk='1' then

	   if mshi="0101" and mge="1001" and sshi="0101" then

	      if sge="0000" or sge="0010" or sge="0100" or sge="0110" or sge="1000" then

		    cp500<='0';

		 else

		    cp500<='1';

		 end if;

	   end if;

	   if mshi="0000" and mge="0000" and sshi="0000" and sge="0000" then

	         cp1000<='0';

	   else

	         cp1000<='1';

	   end if;

	 end if;

   end process;

end Behavioral;

================================================================================================
ch_bcd_integer.vhdl
------------------
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;



entity ch_bcd_integer is

  port(clk:in std_logic;

       h1,h2,f1,f2,m1,m2:in std_logic_vector(3 downto 0);

       d1,d2,d3,d4,d5,d6:out integer range 0 to 9);

end ch_bcd_integer;



architecture Behavioral of ch_bcd_integer is



begin

process(clk)

begin 

    if clk'event and clk='1' then

	    d1<=conv_integer(h2);

	    d2<=conv_integer(h1);

	    d3<=conv_integer(f2);

	    d4<=conv_integer(f1);

	    d5<=conv_integer(m2);

	    d6<=conv_integer(m1);

    end if;

end process;

end Behavioral;
==================================================================
digclk.vhd
---------------------------
library ieee;

use ieee.std_logic_1164.ALL;

use ieee.numeric_std.ALL;

-- synopsys translate_off

library UNISIM;

use UNISIM.Vcomponents.ALL;

-- sy
=>XLXN_38,

                I1=>XLXN_39,

                O=>sound);

   

   XLXI_35 : AND2

      port map (I0=>shour,

                I1=>XLXN_61,

                O=>XLXN_64);

   

   XLXI_36 : AND2

      port map (I0=>smin,

                I1=>XLXN_62,

                O=>XLXN_30);

   

   XLXI_37 : OR2

      port map (I0=>XLXN_63,

                I1=>XLXN_62,

                O=>XLXN_61);

   

   XLXI_38 : LCD1602

      port map (CLK=>clk,

                fg(3 downto 0)=>XLXN_52(3 downto 0),

                fs(3 downto 0)=>XLXN_51(3 downto 0),

                mg(3 downto 0)=>XLXN_54(3 downto 0),

                ms(3 downto 0)=>XLXN_73(3 downto 0),

                Reset=>rst,

                sg(3 downto 0)=>XLXN_49(3 downto 0),

                ss(3 downto 0)=>XLXN_48(3 downto 0),

                LCD_Data(7 downto 0)=>lcd_data(7 downto 0),

                LCD_EN=>lcd_en,

                LCD_RS=>lcd_rs,

                LCD_RW=>lcd_rw);

   

end BEHAVIORAL;
=====================
miao.vhdl
--------------------------------------
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



--  Uncomment the following lines to use the declarations that are

--  provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;



entity miao is

    Port ( CLK : in std_logic;

           CLR:  in std_logic;

		 ZANTING: in std_logic;

		 COUT: out std_logic;

           SECSHI,SECGE : out std_logic_vector(3 downto 0));

end miao;



architecture Behavioral of miao is

begin

 process (CLR,ZANTING,CLK)

  VARIABLE CNT1,CNT0:STD_LOGIC_VECTOR(3 DOWNTO 0); 
  begin
   IF CLR='1'THEN 

         CNT1:="0000";

	    CNT0:="0000";

   ELSIF ZANTING='1'THEN

	    CNT0:=CNT0;
   ELSIF CLK='1' AND  CLK'event THEN
      IF CNT1="0101" AND CNT0="1000" THEN

	    CNT0:="1001";

	    COUT<='1';
      ELSIF CNT0<"1001" THEN 
         CNT0:=CNT0+1;

	 ELSE    

	    CNT0:="0000";

	    IF CNT1<"0101" THEN

	       CNT1:=CNT1+1;

	    ELSE

	       CNT1:="0000";

		  COUT<='0';
      END IF;
    END IF;

  END IF;

        SECSHI<=CNT1;

	   SECGE<=CNT0;
end process;

end Behavioral;

======================