myadder.v

来自「基于ALTERA 公司cyclone系列FPGA的程序」· Verilog 代码 · 共 17 行

module myadder(
               a,
               b,
               carry_in,
               sum,
               carry_out
               );

input   a,b,carry_in;
output  sum,carry_out;

wire    a,b,carry_in;
wire    sum,carry_out;

assign { carry_out,sum}=a+b+carry_in;

endmodule