adder4.v

来自「基于ALTERA 公司cyclone系列FPGA的程序」· Verilog 代码 · 共 29 行

module adder4(
              a,
              b,
              carry_in,
              sum,
              carry_out
              );

input   [3:0]  a,b;
input          carry_in;
output  [3:0]  sum;
output         carry_out;

wire    [3:0]  a,b;
wire           carry_in;
wire    [3:0]  sum;
wire           carry_out;

wire           carry_out0;
wire           carry_out1;
wire           carry_out2;

myadder adder0(a[0],b[0],carry_in,
               sum[0],carry_out0);
mydecr  decr0 (a[1],b[1],carryout0,
               sum[1],caryout1);


endmodule