myadder.map.qmsg

基于ALTERA 公司cyclone系列FPGA的程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 23 14:36:08 2007 " "Info: Processing started: Mon Jul 23 14:36:08 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myadder -c myadder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myadder -c myadder" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mypll2_bb.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mypll2_bb.v" { { "Info" "ISGN_ENTITY_NAME" "1 mypll2 " "Info: Found entity 1: mypll2" {  } { { "mypll2_bb.v" "" { Text "D:/program/FPGA/adder/mypll2_bb.v" 31 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "ESGN_DUPLICATE_ENTITY" "mypll2 mypll2_bb.v mypll2.v " "Error: Entity \"mypll2\" in file mypll2_bb.v already exists in file mypll2.v" {  } { { "mypll2_bb.v" "" { Text "D:/program/FPGA/adder/mypll2_bb.v" 31 -1 0 } } { "mypll2.v" "" { Text "D:/program/FPGA/adder/mypll2.v" 36 -1 0 } }  } 0 0 "Entity \"%1!s!\" in file %2!s! already exists in file %3!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mypll2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mypll2.v" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mypll.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mypll.v" { { "Info" "ISGN_ENTITY_NAME" "1 mypll " "Info: Found entity 1: mypll" {  } { { "mypll.v" "" { Text "D:/program/FPGA/adder/mypll.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "ESGN_DUPLICATE_ENTITY" "mypll mypll.v mypll_bb.v " "Error: Entity \"mypll\" in file mypll.v already exists in file mypll_bb.v" {  } { { "mypll.v" "" { Text "D:/program/FPGA/adder/mypll.v" 36 -1 0 } } { "mypll_bb.v" "" { Text "D:/program/FPGA/adder/mypll_bb.v" 31 -1 0 } }  } 0 0 "Entity \"%1!s!\" in file %2!s! already exists in file %3!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mypll_bb.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mypll_bb.v" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "myadder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file myadder.v" { { "Info" "ISGN_ENTITY_NAME" "1 myadder " "Info: Found entity 1: myadder" {  } { { "myadder.v" "" { Text "D:/program/FPGA/adder/myadder.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "carryout0 adder4.v(25) " "Warning (10236): Verilog HDL net warning at adder4.v(25): created undeclared net \"carryout0\"" {  } { { "adder4.v" "" { Text "D:/program/FPGA/adder/adder4.v" 25 0 0 } }  } 0 10236 "Verilog HDL net warning at %2!s!: created undeclared net \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "caryout1 adder4.v(26) " "Warning (10236): Verilog HDL net warning at adder4.v(26): created undeclared net \"caryout1\"" {  } { { "adder4.v" "" { Text "D:/program/FPGA/adder/adder4.v" 26 0 0 } }  } 0 10236 "Verilog HDL net warning at %2!s!: created undeclared net \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder4.v" { { "Info" "ISGN_ENTITY_NAME" "1 adder4 " "Info: Found entity 1: adder4" {  } { { "adder4.v" "" { Text "D:/program/FPGA/adder/adder4.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mydecr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mydecr.v" { { "Info" "ISGN_ENTITY_NAME" "1 mydecr " "Info: Found entity 1: mydecr" {  } { { "mydecr.v" "" { Text "D:/program/FPGA/adder/mydecr.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "D:/program/FPGA/adder/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 2 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 2 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Mon Jul 23 14:36:09 2007 " "Error: Processing ended: Mon Jul 23 14:36:09 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}