myadder.hif

基于ALTERA 公司cyclone系列FPGA的程序

Version 6.0 Build 178 04/27/2006 SJ Full Version
35
1750
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
myadder
# storage
db|myadder.(0).cnf
db|myadder.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
myadder.v
506fe6bddea4b3e85df9b7b5958994
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
myadder:adder0
}
# end
# entity
adder4
# storage
db|myadder.(1).cnf
db|myadder.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
adder4.v
f0ebf3a9eded891c27696f1a9f6231cf
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
mydecr
# storage
db|myadder.(2).cnf
db|myadder.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
mydecr.v
8512ebedda67715e60675c1dbef6451
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mydecr:decr0
}
# end
# complete