myadder.hier_info

基于ALTERA 公司cyclone系列FPGA的程序

|adder4
a[0] => a[0]~1.IN1
a[1] => a[1]~0.IN1
a[2] => ~NO_FANOUT~
a[3] => ~NO_FANOUT~
b[0] => b[0]~1.IN1
b[1] => b[1]~0.IN1
b[2] => ~NO_FANOUT~
b[3] => ~NO_FANOUT~
carry_in => carry_in~0.IN1
sum[0] <= myadder:adder0.port3
sum[1] <= mydecr:decr0.port3
sum[2] <= <GND>
sum[3] <= <GND>
carry_out <= <GND>


|adder4|myadder:adder0
a => Add0.IN1
b => Add0.IN2
carry_in => Add1.IN4
sum <= Add1.DB_MAX_OUTPUT_PORT_TYPE
carry_out <= Add1.DB_MAX_OUTPUT_PORT_TYPE


|adder4|mydecr:decr0
a => Add0.IN2
b => Add0.IN1
carry_in => Add1.IN4
sum <= Add1.DB_MAX_OUTPUT_PORT_TYPE
carry_out <= Add1.DB_MAX_OUTPUT_PORT_TYPE