📄 myadder_modelsim.xrf
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vendor_name = ModelSim
source_file = 1, D:/program/FPGA/adder/adder4.bsf
source_file = 1, D:/program/FPGA/adder/myadder.v
source_file = 1, D:/program/FPGA/adder/adder4.v
source_file = 1, D:/program/FPGA/adder/mydecr.v
design_name = adder4
instance = comp, \a[0]~I , a[0], adder4, 1
instance = comp, \carry_in~I , carry_in, adder4, 1
instance = comp, \b[0]~I , b[0], adder4, 1
instance = comp, \adder0|Add1~23_I , adder0|Add1~23, adder4, 1
instance = comp, \a[1]~I , a[1], adder4, 1
instance = comp, \b[1]~I , b[1], adder4, 1
instance = comp, \decr0|Add0~15_I , decr0|Add0~15, adder4, 1
instance = comp, \a[2]~I , a[2], adder4, 1
instance = comp, \a[3]~I , a[3], adder4, 1
instance = comp, \b[2]~I , b[2], adder4, 1
instance = comp, \b[3]~I , b[3], adder4, 1
instance = comp, \sum[0]~I , sum[0], adder4, 1
instance = comp, \sum[1]~I , sum[1], adder4, 1
instance = comp, \sum[2]~I , sum[2], adder4, 1
instance = comp, \sum[3]~I , sum[3], adder4, 1
instance = comp, \carry_out~I , carry_out, adder4, 1
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