myadder.vo

基于ALTERA 公司cyclone系列FPGA的程序

// atom is at PIN_174
cyclone_io \a[2]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(a[2]));
// synopsys translate_off
defparam \a[2]~I .input_async_reset = "none";
defparam \a[2]~I .input_power_up = "low";
defparam \a[2]~I .input_register_mode = "none";
defparam \a[2]~I .input_sync_reset = "none";
defparam \a[2]~I .oe_async_reset = "none";
defparam \a[2]~I .oe_power_up = "low";
defparam \a[2]~I .oe_register_mode = "none";
defparam \a[2]~I .oe_sync_reset = "none";
defparam \a[2]~I .operation_mode = "input";
defparam \a[2]~I .output_async_reset = "none";
defparam \a[2]~I .output_power_up = "low";
defparam \a[2]~I .output_register_mode = "none";
defparam \a[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_199
cyclone_io \a[3]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(a[3]));
// synopsys translate_off
defparam \a[3]~I .input_async_reset = "none";
defparam \a[3]~I .input_power_up = "low";
defparam \a[3]~I .input_register_mode = "none";
defparam \a[3]~I .input_sync_reset = "none";
defparam \a[3]~I .oe_async_reset = "none";
defparam \a[3]~I .oe_power_up = "low";
defparam \a[3]~I .oe_register_mode = "none";
defparam \a[3]~I .oe_sync_reset = "none";
defparam \a[3]~I .operation_mode = "input";
defparam \a[3]~I .output_async_reset = "none";
defparam \a[3]~I .output_power_up = "low";
defparam \a[3]~I .output_register_mode = "none";
defparam \a[3]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_23
cyclone_io \b[2]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(b[2]));
// synopsys translate_off
defparam \b[2]~I .input_async_reset = "none";
defparam \b[2]~I .input_power_up = "low";
defparam \b[2]~I .input_register_mode = "none";
defparam \b[2]~I .input_sync_reset = "none";
defparam \b[2]~I .oe_async_reset = "none";
defparam \b[2]~I .oe_power_up = "low";
defparam \b[2]~I .oe_register_mode = "none";
defparam \b[2]~I .oe_sync_reset = "none";
defparam \b[2]~I .operation_mode = "input";
defparam \b[2]~I .output_async_reset = "none";
defparam \b[2]~I .output_power_up = "low";
defparam \b[2]~I .output_register_mode = "none";
defparam \b[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_117
cyclone_io \b[3]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(b[3]));
// synopsys translate_off
defparam \b[3]~I .input_async_reset = "none";
defparam \b[3]~I .input_power_up = "low";
defparam \b[3]~I .input_register_mode = "none";
defparam \b[3]~I .input_sync_reset = "none";
defparam \b[3]~I .oe_async_reset = "none";
defparam \b[3]~I .oe_power_up = "low";
defparam \b[3]~I .oe_register_mode = "none";
defparam \b[3]~I .oe_sync_reset = "none";
defparam \b[3]~I .operation_mode = "input";
defparam \b[3]~I .output_async_reset = "none";
defparam \b[3]~I .output_power_up = "low";
defparam \b[3]~I .output_register_mode = "none";
defparam \b[3]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_62
cyclone_io \sum[0]~I (
	.datain(\adder0|Add1~23 ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(sum[0]));
// synopsys translate_off
defparam \sum[0]~I .input_async_reset = "none";
defparam \sum[0]~I .input_power_up = "low";
defparam \sum[0]~I .input_register_mode = "none";
defparam \sum[0]~I .input_sync_reset = "none";
defparam \sum[0]~I .oe_async_reset = "none";
defparam \sum[0]~I .oe_power_up = "low";
defparam \sum[0]~I .oe_register_mode = "none";
defparam \sum[0]~I .oe_sync_reset = "none";
defparam \sum[0]~I .operation_mode = "output";
defparam \sum[0]~I .output_async_reset = "none";
defparam \sum[0]~I .output_power_up = "low";
defparam \sum[0]~I .output_register_mode = "none";
defparam \sum[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_236
cyclone_io \sum[1]~I (
	.datain(\decr0|Add0~15 ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(sum[1]));
// synopsys translate_off
defparam \sum[1]~I .input_async_reset = "none";
defparam \sum[1]~I .input_power_up = "low";
defparam \sum[1]~I .input_register_mode = "none";
defparam \sum[1]~I .input_sync_reset = "none";
defparam \sum[1]~I .oe_async_reset = "none";
defparam \sum[1]~I .oe_power_up = "low";
defparam \sum[1]~I .oe_register_mode = "none";
defparam \sum[1]~I .oe_sync_reset = "none";
defparam \sum[1]~I .operation_mode = "output";
defparam \sum[1]~I .output_async_reset = "none";
defparam \sum[1]~I .output_power_up = "low";
defparam \sum[1]~I .output_register_mode = "none";
defparam \sum[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_84
cyclone_io \sum[2]~I (
	.datain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(sum[2]));
// synopsys translate_off
defparam \sum[2]~I .input_async_reset = "none";
defparam \sum[2]~I .input_power_up = "low";
defparam \sum[2]~I .input_register_mode = "none";
defparam \sum[2]~I .input_sync_reset = "none";
defparam \sum[2]~I .oe_async_reset = "none";
defparam \sum[2]~I .oe_power_up = "low";
defparam \sum[2]~I .oe_register_mode = "none";
defparam \sum[2]~I .oe_sync_reset = "none";
defparam \sum[2]~I .operation_mode = "output";
defparam \sum[2]~I .output_async_reset = "none";
defparam \sum[2]~I .output_power_up = "low";
defparam \sum[2]~I .output_register_mode = "none";
defparam \sum[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_158
cyclone_io \sum[3]~I (
	.datain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(sum[3]));
// synopsys translate_off
defparam \sum[3]~I .input_async_reset = "none";
defparam \sum[3]~I .input_power_up = "low";
defparam \sum[3]~I .input_register_mode = "none";
defparam \sum[3]~I .input_sync_reset = "none";
defparam \sum[3]~I .oe_async_reset = "none";
defparam \sum[3]~I .oe_power_up = "low";
defparam \sum[3]~I .oe_register_mode = "none";
defparam \sum[3]~I .oe_sync_reset = "none";
defparam \sum[3]~I .operation_mode = "output";
defparam \sum[3]~I .output_async_reset = "none";
defparam \sum[3]~I .output_power_up = "low";
defparam \sum[3]~I .output_register_mode = "none";
defparam \sum[3]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_176
cyclone_io \carry_out~I (
	.datain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(carry_out));
// synopsys translate_off
defparam \carry_out~I .input_async_reset = "none";
defparam \carry_out~I .input_power_up = "low";
defparam \carry_out~I .input_register_mode = "none";
defparam \carry_out~I .input_sync_reset = "none";
defparam \carry_out~I .oe_async_reset = "none";
defparam \carry_out~I .oe_power_up = "low";
defparam \carry_out~I .oe_register_mode = "none";
defparam \carry_out~I .oe_sync_reset = "none";
defparam \carry_out~I .operation_mode = "output";
defparam \carry_out~I .output_async_reset = "none";
defparam \carry_out~I .output_power_up = "low";
defparam \carry_out~I .output_register_mode = "none";
defparam \carry_out~I .output_sync_reset = "none";
// synopsys translate_on

endmodule