myadder.vo

基于ALTERA 公司cyclone系列FPGA的程序

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

// DATE "07/23/2007 13:40:32"

// 
// Device: Altera EP1C6Q240C8 Package PQFP240
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module adder4 (
	a,
	b,
	carry_in,
	sum,
	carry_out);
input 	[3:0] a;
input 	[3:0] b;
input 	carry_in;
output 	[3:0] sum;
output 	carry_out;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("myadder_v.sdo");
// synopsys translate_on

wire \carry_in~combout ;
wire \adder0|Add1~23 ;
wire \decr0|Add0~15 ;
wire [3:0] \a~combout ;
wire [3:0] \b~combout ;


// atom is at PIN_240
cyclone_io \a[0]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\a~combout [0]),
	.regout(),
	.padio(a[0]));
// synopsys translate_off
defparam \a[0]~I .input_async_reset = "none";
defparam \a[0]~I .input_power_up = "low";
defparam \a[0]~I .input_register_mode = "none";
defparam \a[0]~I .input_sync_reset = "none";
defparam \a[0]~I .oe_async_reset = "none";
defparam \a[0]~I .oe_power_up = "low";
defparam \a[0]~I .oe_register_mode = "none";
defparam \a[0]~I .oe_sync_reset = "none";
defparam \a[0]~I .operation_mode = "input";
defparam \a[0]~I .output_async_reset = "none";
defparam \a[0]~I .output_power_up = "low";
defparam \a[0]~I .output_register_mode = "none";
defparam \a[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_16
cyclone_io \carry_in~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\carry_in~combout ),
	.regout(),
	.padio(carry_in));
// synopsys translate_off
defparam \carry_in~I .input_async_reset = "none";
defparam \carry_in~I .input_power_up = "low";
defparam \carry_in~I .input_register_mode = "none";
defparam \carry_in~I .input_sync_reset = "none";
defparam \carry_in~I .oe_async_reset = "none";
defparam \carry_in~I .oe_power_up = "low";
defparam \carry_in~I .oe_register_mode = "none";
defparam \carry_in~I .oe_sync_reset = "none";
defparam \carry_in~I .operation_mode = "input";
defparam \carry_in~I .output_async_reset = "none";
defparam \carry_in~I .output_power_up = "low";
defparam \carry_in~I .output_register_mode = "none";
defparam \carry_in~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_14
cyclone_io \b[0]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\b~combout [0]),
	.regout(),
	.padio(b[0]));
// synopsys translate_off
defparam \b[0]~I .input_async_reset = "none";
defparam \b[0]~I .input_power_up = "low";
defparam \b[0]~I .input_register_mode = "none";
defparam \b[0]~I .input_sync_reset = "none";
defparam \b[0]~I .oe_async_reset = "none";
defparam \b[0]~I .oe_power_up = "low";
defparam \b[0]~I .oe_register_mode = "none";
defparam \b[0]~I .oe_sync_reset = "none";
defparam \b[0]~I .operation_mode = "input";
defparam \b[0]~I .output_async_reset = "none";
defparam \b[0]~I .output_power_up = "low";
defparam \b[0]~I .output_register_mode = "none";
defparam \b[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X1_Y16_N4
cyclone_lcell \adder0|Add1~23_I (
// Equation(s):
// \adder0|Add1~23  = \a~combout [0] $ \carry_in~combout  $ (\b~combout [0])

	.clk(gnd),
	.dataa(\a~combout [0]),
	.datab(\carry_in~combout ),
	.datac(vcc),
	.datad(\b~combout [0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\adder0|Add1~23 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \adder0|Add1~23_I .lut_mask = "9966";
defparam \adder0|Add1~23_I .operation_mode = "normal";
defparam \adder0|Add1~23_I .output_mode = "comb_only";
defparam \adder0|Add1~23_I .register_cascade_mode = "off";
defparam \adder0|Add1~23_I .sum_lutc_input = "datac";
defparam \adder0|Add1~23_I .synch_mode = "off";
// synopsys translate_on

// atom is at PIN_237
cyclone_io \a[1]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\a~combout [1]),
	.regout(),
	.padio(a[1]));
// synopsys translate_off
defparam \a[1]~I .input_async_reset = "none";
defparam \a[1]~I .input_power_up = "low";
defparam \a[1]~I .input_register_mode = "none";
defparam \a[1]~I .input_sync_reset = "none";
defparam \a[1]~I .oe_async_reset = "none";
defparam \a[1]~I .oe_power_up = "low";
defparam \a[1]~I .oe_register_mode = "none";
defparam \a[1]~I .oe_sync_reset = "none";
defparam \a[1]~I .operation_mode = "input";
defparam \a[1]~I .output_async_reset = "none";
defparam \a[1]~I .output_power_up = "low";
defparam \a[1]~I .output_register_mode = "none";
defparam \a[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_235
cyclone_io \b[1]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\b~combout [1]),
	.regout(),
	.padio(b[1]));
// synopsys translate_off
defparam \b[1]~I .input_async_reset = "none";
defparam \b[1]~I .input_power_up = "low";
defparam \b[1]~I .input_register_mode = "none";
defparam \b[1]~I .input_sync_reset = "none";
defparam \b[1]~I .oe_async_reset = "none";
defparam \b[1]~I .oe_power_up = "low";
defparam \b[1]~I .oe_register_mode = "none";
defparam \b[1]~I .oe_sync_reset = "none";
defparam \b[1]~I .operation_mode = "input";
defparam \b[1]~I .output_async_reset = "none";
defparam \b[1]~I .output_power_up = "low";
defparam \b[1]~I .output_register_mode = "none";
defparam \b[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X4_Y20_N2
cyclone_lcell \decr0|Add0~15_I (
// Equation(s):
// \decr0|Add0~15  = \a~combout [1] $ (\b~combout [1])

	.clk(gnd),
	.dataa(vcc),
	.datab(\a~combout [1]),
	.datac(vcc),
	.datad(\b~combout [1]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\decr0|Add0~15 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \decr0|Add0~15_I .lut_mask = "33CC";
defparam \decr0|Add0~15_I .operation_mode = "normal";
defparam \decr0|Add0~15_I .output_mode = "comb_only";
defparam \decr0|Add0~15_I .register_cascade_mode = "off";
defparam \decr0|Add0~15_I .sum_lutc_input = "datac";
defparam \decr0|Add0~15_I .synch_mode = "off";
// synopsys translate_on