📄 colorbar_v.sdo
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// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP1C12Q240C8 Package PQFP240
//
//
// This SDF file should be used for ModelSim (Verilog) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "ColorBar")
(DATE "04/01/2006 12:16:08")
(VENDOR "Altera")
(PROGRAM "Quartus II")
(VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cyclone_asynch_io")
(INSTANCE clk\~I.asynch_inst)
(DELAY
(ABSOLUTE
(IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
)
)
)
(CELL
(CELLTYPE "cyclone_pll")
(INSTANCE inst4\|altpll_component\|pll)
(DELAY
(ABSOLUTE
(PORT inclk[0] (1846:1846:1846) (1846:1846:1846))
)
)
)
(CELL
(CELLTYPE "cyclone_asynch_io")
(INSTANCE rst\~I.asynch_inst)
(DELAY
(ABSOLUTE
(IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
)
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE inst\|hcnt\[0\]\~I.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (516:516:516) (521:521:521))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH datab cout0 (423:423:423) (423:423:423))
(IOPATH datab cout1 (432:432:432) (432:432:432))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE inst\|hcnt\[0\]\~I.lereg)
(DELAY
(ABSOLUTE
(PORT sclr (1530:1530:1530) (1587:1587:1587))
(PORT aclr (1462:1462:1462) (1442:1442:1442))
(PORT clk (2464:2464:2464) (2444:2444:2444))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(SETUP sclr (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
(HOLD sclr (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE inst\|hcnt\[1\]\~I.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (542:542:542) (546:546:546))
(IOPATH dataa regin (738:738:738) (738:738:738))
(IOPATH cin0 regin (783:783:783) (783:783:783))
(IOPATH cin1 regin (787:787:787) (787:787:787))
(IOPATH dataa cout0 (564:564:564) (564:564:564))
(IOPATH cin0 cout0 (78:78:78) (78:78:78))
(IOPATH dataa cout1 (575:575:575) (575:575:575))
(IOPATH cin1 cout1 (80:80:80) (80:80:80))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE inst\|hcnt\[1\]\~I.lereg)
(DELAY
(ABSOLUTE
(PORT sclr (1530:1530:1530) (1587:1587:1587))
(PORT aclr (1462:1462:1462) (1442:1442:1442))
(PORT clk (2464:2464:2464) (2444:2444:2444))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(SETUP sclr (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
(HOLD sclr (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE inst\|hcnt\[2\]\~I.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (554:554:554) (556:556:556))
(IOPATH dataa regin (738:738:738) (738:738:738))
(IOPATH cin0 regin (783:783:783) (783:783:783))
(IOPATH cin1 regin (787:787:787) (787:787:787))
(IOPATH dataa cout0 (564:564:564) (564:564:564))
(IOPATH cin0 cout0 (78:78:78) (78:78:78))
(IOPATH dataa cout1 (575:575:575) (575:575:575))
(IOPATH cin1 cout1 (80:80:80) (80:80:80))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE inst\|hcnt\[2\]\~I.lereg)
(DELAY
(ABSOLUTE
(PORT sclr (1530:1530:1530) (1587:1587:1587))
(PORT aclr (1462:1462:1462) (1442:1442:1442))
(PORT clk (2464:2464:2464) (2444:2444:2444))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(SETUP sclr (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
(HOLD sclr (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE inst\|hcnt\[3\]\~I.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (518:518:518) (525:525:525))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH cin0 regin (783:783:783) (783:783:783))
(IOPATH cin1 regin (787:787:787) (787:787:787))
(IOPATH datab cout0 (423:423:423) (423:423:423))
(IOPATH cin0 cout0 (78:78:78) (78:78:78))
(IOPATH datab cout1 (432:432:432) (432:432:432))
(IOPATH cin1 cout1 (80:80:80) (80:80:80))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE inst\|hcnt\[3\]\~I.lereg)
(DELAY
(ABSOLUTE
(PORT sclr (1530:1530:1530) (1587:1587:1587))
(PORT aclr (1462:1462:1462) (1442:1442:1442))
(PORT clk (2464:2464:2464) (2444:2444:2444))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(SETUP sclr (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
(HOLD sclr (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE inst\|hcnt\[4\]\~I.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (546:546:546) (552:552:552))
(IOPATH dataa regin (738:738:738) (738:738:738))
(IOPATH cin0 regin (783:783:783) (783:783:783))
(IOPATH cin1 regin (787:787:787) (787:787:787))
(IOPATH dataa cout (838:838:838) (838:838:838))
(IOPATH cin0 cout (271:271:271) (271:271:271))
(IOPATH cin1 cout (258:258:258) (258:258:258))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE inst\|hcnt\[4\]\~I.lereg)
(DELAY
(ABSOLUTE
(PORT sclr (1530:1530:1530) (1587:1587:1587))
(PORT aclr (1462:1462:1462) (1442:1442:1442))
(PORT clk (2464:2464:2464) (2444:2444:2444))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(SETUP sclr (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
(HOLD sclr (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE inst\|hcnt\[5\]\~I.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (538:538:538) (534:534:534))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH cin regin (898:898:898) (898:898:898))
(IOPATH datab cout0 (423:423:423) (423:423:423))
(IOPATH datab cout1 (432:432:432) (432:432:432))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE inst\|hcnt\[5\]\~I.lereg)
(DELAY
(ABSOLUTE
(PORT sclr (2249:2249:2249) (2349:2349:2349))
(PORT aclr (1462:1462:1462) (1442:1442:1442))
(PORT clk (2464:2464:2464) (2444:2444:2444))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(SETUP sclr (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
(HOLD sclr (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE inst\|hcnt\[6\]\~I.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (541:541:541) (546:546:546))
(IOPATH dataa regin (738:738:738) (738:738:738))
(IOPATH cin regin (898:898:898) (898:898:898))
(IOPATH cin0 regin (783:783:783) (783:783:783))
(IOPATH cin1 regin (787:787:787) (787:787:787))
(IOPATH dataa cout0 (564:564:564) (564:564:564))
(IOPATH cin0 cout0 (78:78:78) (78:78:78))
(IOPATH dataa cout1 (575:575:575) (575:575:575))
(IOPATH cin1 cout1 (80:80:80) (80:80:80))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE inst\|hcnt\[6\]\~I.lereg)
(DELAY
(ABSOLUTE
(PORT sclr (2249:2249:2249) (2349:2349:2349))
(PORT aclr (1462:1462:1462) (1442:1442:1442))
(PORT clk (2464:2464:2464) (2444:2444:2444))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(SETUP sclr (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
(HOLD sclr (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE inst\|hcnt\[7\]\~I.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (564:564:564) (562:562:562))
(IOPATH dataa regin (738:738:738) (738:738:738))
(IOPATH cin regin (898:898:898) (898:898:898))
(IOPATH cin0 regin (783:783:783) (783:783:783))
(IOPATH cin1 regin (787:787:787) (787:787:787))
(IOPATH dataa cout0 (564:564:564) (564:564:564))
(IOPATH cin0 cout0 (78:78:78) (78:78:78))
(IOPATH dataa cout1 (575:575:575) (575:575:575))
(IOPATH cin1 cout1 (80:80:80) (80:80:80))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE inst\|hcnt\[7\]\~I.lereg)
(DELAY
(ABSOLUTE
(PORT sclr (2249:2249:2249) (2349:2349:2349))
(PORT aclr (1462:1462:1462) (1442:1442:1442))
(PORT clk (2464:2464:2464) (2444:2444:2444))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(SETUP sclr (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
(HOLD sclr (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE inst\|hcnt\[8\]\~I.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (549:549:549) (547:547:547))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH cin regin (898:898:898) (898:898:898))
(IOPATH cin0 regin (783:783:783) (783:783:783))
(IOPATH cin1 regin (787:787:787) (787:787:787))
(IOPATH datab cout0 (423:423:423) (423:423:423))
(IOPATH cin0 cout0 (78:78:78) (78:78:78))
(IOPATH datab cout1 (432:432:432) (432:432:432))
(IOPATH cin1 cout1 (80:80:80) (80:80:80))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE inst\|hcnt\[8\]\~I.lereg)
(DELAY
(ABSOLUTE
(PORT sclr (2249:2249:2249) (2349:2349:2349))
(PORT aclr (1462:1462:1462) (1442:1442:1442))
(PORT clk (2464:2464:2464) (2444:2444:2444))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(SETUP sclr (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
(HOLD sclr (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE inst\|LessThan\~4981_I.lecomb)
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