vga_test.v

verilog源代码

`timescale 1ns/1ps
`include"vga_vl.v"
module vga_test;
    reg clock,resetn,orient;
    wire hsync,vsync,blank;
    wire [2:0] pixel;
    always #10 clock=~clock;
    initial 
    begin
        resetn=1;clock=0;orient=0;
        #100 resetn=0;
        #100 resetn=1;
        #2500000 orient=1;
        #2500000 $stop;
    end
    vga_vl vga(.clock(clock),.resetn(resetn),.hsync(hsync),.vsync(vsync),.pixel(pixel),.blank(blank)); 
endmodule