_primary.vhd

来自「verilog源代码」· VHDL 代码 · 共 30 行

library verilog;
use verilog.vl_types.all;
entity vga_vl is
    generic(
        H_PIXELS        : integer := 806;
        H_FRONTPORCH    : integer := 37;
        H_SYNCTIME      : integer := 128;
        H_BACKPORCH     : integer := 85;
        H_SYNCSTART     : integer := 843;
        H_SYNCEND       : integer := 971;
        H_PERIOD        : integer := 1056;
        V_LINES         : integer := 604;
        V_FRONTPORCH    : integer := -1;
        V_SYNCTIME      : integer := 4;
        V_BACKPORCH     : integer := 21;
        V_SYNCSTART     : integer := 603;
        V_SYNCEND       : integer := 607;
        V_PERIOD        : integer := 628
    );
    port(
        resetn          : in     vl_logic;
        clock           : in     vl_logic;
        orient          : in     vl_logic;
        hsync           : out    vl_logic;
        vsync           : out    vl_logic;
        pixel           : out    vl_logic_vector(2 downto 0);
        blank           : out    vl_logic
    );
end vga_vl;