cam.map.qmsg

用VHDL编写的程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 18 16:52:03 2005 " "Info: Processing started: Fri Nov 18 16:52:03 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cam -c cam " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cam -c cam" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cam.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cam.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cam-behavioural " "Info: Found design unit 1: cam-behavioural" {  } { { "cam.vhd" "" { Text "C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cam " "Info: Found entity 1: cam" {  } { { "cam.vhd" "" { Text "C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cam " "Info: Elaborating entity \"cam\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "addr cam.vhd(57) " "Info: (10035) Verilog HDL or VHDL information at cam.vhd(57): object \"addr\" declared but not used" {  } { { "cam.vhd" "" { Text "C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd" 57 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "139 " "Info: Implemented 139 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "22 " "Info: Implemented 22 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "113 " "Info: Implemented 113 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 18 16:52:06 2005 " "Info: Processing ended: Fri Nov 18 16:52:06 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}