cam.tan.qmsg

用VHDL编写的程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk data_out\[1\] data_out\[1\]~reg0 6.265 ns register " "Info: tco from clock \"clk\" to destination pin \"data_out\[1\]\" through register \"data_out\[1\]~reg0\" is 6.265 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.658 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 47 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 47; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "" { clk } "NODE_NAME" } "" } } { "cam.vhd" "" { Text "C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(0.000 ns) 1.658 ns data_out\[1\]~reg0 2 REG LC10_9_D2 1 " "Info: 2: + IC(0.768 ns) + CELL(0.000 ns) = 1.658 ns; Loc. = LC10_9_D2; Fanout = 1; REG Node = 'data_out\[1\]~reg0'" {  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "0.768 ns" { clk data_out[1]~reg0 } "NODE_NAME" } "" } } { "cam.vhd" "" { Text "C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.68 % " "Info: Total cell delay = 0.890 ns ( 53.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.768 ns 46.32 % " "Info: Total interconnect delay = 0.768 ns ( 46.32 % )" {  } {  } 0}  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "1.658 ns" { clk data_out[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.658 ns" { clk clk~out0 data_out[1]~reg0 } { 0.000ns 0.000ns 0.768ns } { 0.000ns 0.890ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "cam.vhd" "" { Text "C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.272 ns + Longest register pin " "Info: + Longest register to pin delay is 4.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns data_out\[1\]~reg0 1 REG LC10_9_D2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC10_9_D2; Fanout = 1; REG Node = 'data_out\[1\]~reg0'" {  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "" { data_out[1]~reg0 } "NODE_NAME" } "" } } { "cam.vhd" "" { Text "C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.701 ns) + CELL(2.410 ns) 4.272 ns data_out\[1\] 2 PIN PIN_33 0 " "Info: 2: + IC(1.701 ns) + CELL(2.410 ns) = 4.272 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'data_out\[1\]'" {  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "4.111 ns" { data_out[1]~reg0 data_out[1] } "NODE_NAME" } "" } } { "cam.vhd" "" { Text "C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.571 ns 60.18 % " "Info: Total cell delay = 2.571 ns ( 60.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.701 ns 39.82 % " "Info: Total interconnect delay = 1.701 ns ( 39.82 % )" {  } {  } 0}  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "4.272 ns" { data_out[1]~reg0 data_out[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.272 ns" { data_out[1]~reg0 data_out[1] } { 0.000ns 1.701ns } { 0.161ns 2.410ns } } }  } 0}  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "1.658 ns" { clk data_out[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.658 ns" { clk clk~out0 data_out[1]~reg0 } { 0.000ns 0.000ns 0.768ns } { 0.000ns 0.890ns 0.000ns } } } { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "4.272 ns" { data_out[1]~reg0 data_out[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.272 ns" { data_out[1]~reg0 data_out[1] } { 0.000ns 1.701ns } { 0.161ns 2.410ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "data_out\[1\]~reg0 rst clk -1.866 ns register " "Info: th for register \"data_out\[1\]~reg0\" (data pin = \"rst\", clock pin = \"clk\") is -1.866 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.658 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 47 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 47; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "" { clk } "NODE_NAME" } "" } } { "cam.vhd" "" { Text "C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(0.000 ns) 1.658 ns data_out\[1\]~reg0 2 REG LC10_9_D2 1 " "Info: 2: + IC(0.768 ns) + CELL(0.000 ns) = 1.658 ns; Loc. = LC10_9_D2; Fanout = 1; REG Node = 'data_out\[1\]~reg0'" {  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "0.768 ns" { clk data_out[1]~reg0 } "NODE_NAME" } "" } } { "cam.vhd" "" { Text "C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.68 % " "Info: Total cell delay = 0.890 ns ( 53.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.768 ns 46.32 % " "Info: Total interconnect delay = 0.768 ns ( 46.32 % )" {  } {  } 0}  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "1.658 ns" { clk data_out[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.658 ns" { clk clk~out0 data_out[1]~reg0 } { 0.000ns 0.000ns 0.768ns } { 0.000ns 0.890ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.364 ns + " "Info: + Micro hold delay of destination is 0.364 ns" {  } { { "cam.vhd" "" { Text "C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.888 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.960 ns) 0.960 ns rst 1 PIN PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(0.960 ns) = 0.960 ns; Loc. = PIN_127; Fanout = 46; PIN Node = 'rst'" {  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "" { rst } "NODE_NAME" } "" } } { "cam.vhd" "" { Text "C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd" 43 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.354 ns) + CELL(0.798 ns) 3.112 ns rtl~10 2 COMB LC3_9_D2 2 " "Info: 2: + IC(1.354 ns) + CELL(0.798 ns) = 3.112 ns; Loc. = LC3_9_D2; Fanout = 2; COMB Node = 'rtl~10'" {  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "2.152 ns" { rst rtl~10 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.509 ns) 3.888 ns data_out\[1\]~reg0 3 REG LC10_9_D2 1 " "Info: 3: + IC(0.267 ns) + CELL(0.509 ns) = 3.888 ns; Loc. = LC10_9_D2; Fanout = 1; REG Node = 'data_out\[1\]~reg0'" {  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "0.776 ns" { rtl~10 data_out[1]~reg0 } "NODE_NAME" } "" } } { "cam.vhd" "" { Text "C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.267 ns 58.31 % " "Info: Total cell delay = 2.267 ns ( 58.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.621 ns 41.69 % " "Info: Total interconnect delay = 1.621 ns ( 41.69 % )" {  } {  } 0}  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "3.888 ns" { rst rtl~10 data_out[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.888 ns" { rst rst~out0 rtl~10 data_out[1]~reg0 } { 0.000ns 0.000ns 1.354ns 0.267ns } { 0.000ns 0.960ns 0.798ns 0.509ns } } }  } 0}  } { { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "1.658 ns" { clk data_out[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.658 ns" { clk clk~out0 data_out[1]~reg0 } { 0.000ns 0.000ns 0.768ns } { 0.000ns 0.890ns 0.000ns } } } { "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" "" { Report "C:/Documents and Settings/yoyo/桌面/CAM/db/cam_cmp.qrpt" Compiler "cam" "UNKNOWN" "V1" "C:/Documents and Settings/yoyo/桌面/CAM/db/cam.quartus_db" { Floorplan "C:/Documents and Settings/yoyo/桌面/CAM/" "" "3.888 ns" { rst rtl~10 data_out[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.888 ns" { rst rst~out0 rtl~10 data_out[1]~reg0 } { 0.000ns 0.000ns 1.354ns 0.267ns } { 0.000ns 0.960ns 0.798ns 0.509ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 18 16:52:16 2005 " "Info: Processing ended: Fri Nov 18 16:52:16 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}