cam.fit.summary

用VHDL编写的程序

Flow Status : Successful - Fri Nov 18 16:52:11 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : cam
Top-level Entity Name : cam
Family : APEX20KE
Met timing requirements : N/A
Total logic elements : 113 / 1,200 ( 9 % )
Total pins : 26 / 92 ( 28 % )
Total virtual pins : 0
Total memory bits : 0 / 24,576 ( 0 % )
Total PLLs : 0
Device : EP20K30ETC144-1
Timing Models : Final