top_modelsim.do

fpga模拟以太网物理层的源代码

#/////////////////////////////////////////////////////////////////////
#///                                                              ////
#///  top_modelsim.do                                             ////
#///                                                              ////
#///  This file is part of the Ethernet IP core project           ////
#///  http://www.opencores.org/cores/ethmac/                      ////
#///                                                              ////
#///  Author(s):                                                  ////
#///      - Igor Mohor ([e-mail])                      ////
#///                                                              ////
#///  All additional information is avaliable in the Readme.txt   ////
#///  file.                                                       ////
#///                                                              ////
#/////////////////////////////////////////////////////////////////////
#///                                                              ////
#/// Copyright (C) 2001 Authors                                   ////
#///                                                              ////
#/// This source file may be used and distributed without         ////
#/// restriction provided that this copyright statement is not    ////
#/// removed from the file and that any derivative work contains  ////
#/// the original copyright notice and the associated disclaimer. ////
#///                                                              ////
#/// This source file is free software; you can redistribute it   ////
#/// and/or modify it under the terms of the GNU Lesser General   ////
#/// Public License as published by the Free Software Foundation; ////
#/// either version 2.1 of the License, or (at your option) any   ////
#/// later version.                                               ////
#///                                                              ////
#/// This source is distributed in the hope that it will be       ////
#/// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
#/// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
#/// PURPOSE.  See the GNU Lesser General Public License for more ////
#/// details.                                                     ////
#///                                                              ////
#/// You should have received a copy of the GNU Lesser General    ////
#/// Public License along with this source; if not, download it   ////
#/// from http://www.opencores.org/lgpl.shtml                     ////
#///                                                              ////
#/////////////////////////////////////////////////////////////////////
#/
#/ CVS Revision History
#/
#/ $Log: top_modelsim.do,v $
#/ Revision 1.6  2001/11/14 10:19:45  mohor
#/ Generic memory used.
#/
#/ Revision 1.5  2001/10/19 08:55:49  mohor
#/ eth_timescale.v changed to timescale.v This is done because of the
#/ simulation of the few cores in a one joined project.
#/
#/
#/
#/
#/

vlog -reportprogress 300 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_sync_clk1_clk2.v}
vlog -reportprogress 300 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_wishbonedma.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_crc.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_defines.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_maccontrol.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_macstatus.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_miim.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_outputcontrol.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_random.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_receivecontrol.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_register.v}
vlog -reportprogress 300 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_registers.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_rxcounters.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_rxethmac.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_rxstatem.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_shiftreg.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/timescale.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_top.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_transmitcontrol.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_txcounters.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_txethmac.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_txstatem.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/rtl/verilog/eth_clockgen.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/sim/rtl_sim/src/glbl.v}
vlog -reportprogress 300 -work work {C:/cvsroot/ethernet/rtl/verilog/generic_tpram.v}
vlog -reportprogress 300 -work work {C:/cvsroot/ethernet/bench/verilog/tb_eth_top.v}
vlog -reportprogress 30 -work work {C:/cvsroot/ethernet/sim/rtl_sim/src/RAMB4_S16_S16.v}
vlog -reportprogress 300 -work work {C:/cvsroot/ethernet/sim/rtl_sim/src/art_hsdp_256x40.v}




vsim work.glbl work.tb_eth_top

add wave -radix hex  /tb_eth_top/*
add wave -radix hex  /tb_eth_top/ethtop/wbdma/*
add wave -radix hex  /tb_eth_top/ethtop/ethreg1/*
run -all