proj.tan.qmsg

采用vhdl语言编写的16x2液晶显示模块的驱动程序。在quartus中编译完成

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "23 " "Warning: Found 23 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div16:inst2\|count\[3\] " "Info: Detected ripple clock \"div16:inst2\|count\[3\]\" as buffer" {  } { { "../src/div16.v" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/div16.v" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "div16:inst2\|count\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[5\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[5\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[5\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[6\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[6\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[6\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[3\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[3\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[4\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[4\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[4\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[9\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[9\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[9\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[10\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[10\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[10\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[8\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[8\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[8\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[7\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[7\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[7\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[14\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[14\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[14\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[11\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[11\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[11\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[13\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[13\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[13\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[12\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[12\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[12\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[1\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[1\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[2\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[2\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[15\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[15\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[15\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[0\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[0\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[0\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|reduce_nor~378 " "Info: Detected gated clock \"lcd:inst\|reduce_nor~378\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|reduce_nor~378" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|reduce_nor~377 " "Info: Detected gated clock \"lcd:inst\|reduce_nor~377\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|reduce_nor~377" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|reduce_nor~376 " "Info: Detected gated clock \"lcd:inst\|reduce_nor~376\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|reduce_nor~376" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|reduce_nor~379 " "Info: Detected gated clock \"lcd:inst\|reduce_nor~379\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|reduce_nor~379" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkdiv " "Info: Detected ripple clock \"lcd:inst\|clkdiv\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkdiv" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clk_int " "Info: Detected ripple clock \"lcd:inst\|clk_int\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clk_int" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lcd:inst\|state\[2\] register lcd:inst\|state\[4\] 151.1 MHz 6.618 ns Internal " "Info: Clock \"clk\" has Internal fmax of 151.1 MHz between source register \"lcd:inst\|state\[2\]\" and destination register \"lcd:inst\|state\[4\]\" (period= 6.618 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.314 ns + Longest register register " "Info: + Longest register to register delay is 5.314 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|state\[2\] 1 REG LCFF_X18_Y2_N7 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y2_N7; Fanout = 8; REG Node = 'lcd:inst\|state\[2\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { lcd:inst|state[2] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.769 ns) + CELL(0.378 ns) 1.147 ns lcd:inst\|reduce_nor~372 2 COMB LCCOMB_X18_Y2_N22 3 " "Info: 2: + IC(0.769 ns) + CELL(0.378 ns) = 1.147 ns; Loc. = LCCOMB_X18_Y2_N22; Fanout = 3; COMB Node = 'lcd:inst\|reduce_nor~372'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.147 ns" { lcd:inst|state[2] lcd:inst|reduce_nor~372 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.382 ns) + CELL(0.636 ns) 2.165 ns lcd:inst\|reduce_nor~16 3 COMB LCCOMB_X18_Y2_N4 8 " "Info: 3: + IC(0.382 ns) + CELL(0.636 ns) = 2.165 ns; Loc. = LCCOMB_X18_Y2_N4; Fanout = 8; COMB Node = 'lcd:inst\|reduce_nor~16'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.018 ns" { lcd:inst|reduce_nor~372 lcd:inst|reduce_nor~16 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.636 ns) 3.526 ns lcd:inst\|Select~259 4 COMB LCCOMB_X18_Y2_N28 1 " "Info: 4: + IC(0.725 ns) + CELL(0.636 ns) = 3.526 ns; Loc. = LCCOMB_X18_Y2_N28; Fanout = 1; COMB Node = 'lcd:inst\|Select~259'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.361 ns" { lcd:inst|reduce_nor~16 lcd:inst|Select~259 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.042 ns) + CELL(0.636 ns) 5.204 ns lcd:inst\|Select~260 5 COMB LCCOMB_X18_Y2_N20 1 " "Info: 5: + IC(1.042 ns) + CELL(0.636 ns) = 5.204 ns; Loc. = LCCOMB_X18_Y2_N20; Fanout = 1; COMB Node = 'lcd:inst\|Select~260'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.678 ns" { lcd:inst|Select~259 lcd:inst|Select~260 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.110 ns) 5.314 ns lcd:inst\|state\[4\] 6 REG LCFF_X18_Y2_N21 6 " "Info: 6: + IC(0.000 ns) + CELL(0.110 ns) = 5.314 ns; Loc. = LCFF_X18_Y2_N21; Fanout = 6; REG Node = 'lcd:inst\|state\[4\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.110 ns" { lcd:inst|Select~260 lcd:inst|state[4] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.396 ns 45.09 % " "Info: Total cell delay = 2.396 ns ( 45.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.918 ns 54.91 % " "Info: Total interconnect delay = 2.918 ns ( 54.91 % )" {  } {  } 0}  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "5.314 ns" { lcd:inst|state[2] lcd:inst|reduce_nor~372 lcd:inst|reduce_nor~16 lcd:inst|Select~259 lcd:inst|Select~260 lcd:inst|state[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.314 ns" { lcd:inst|state[2] lcd:inst|reduce_nor~372 lcd:inst|reduce_nor~16 lcd:inst|Select~259 lcd:inst|Select~260 lcd:inst|state[4] } { 0.000ns 0.769ns 0.382ns 0.725ns 1.042ns 0.000ns } { 0.000ns 0.378ns 0.636ns 0.636ns 0.636ns 0.110ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.034 ns - Smallest " "Info: - Smallest clock skew is -1.034 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 15.108 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 15.108 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP2C20/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.217 ns clk~clkctrl 2 COMB CLKCTRL_G14 4 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G14; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.117 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP2C20/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.989 ns) 3.295 ns div16:inst2\|count\[3\] 3 REG LCFF_X25_Y2_N1 2 " "Info: 3: + IC(1.089 ns) + CELL(0.989 ns) = 3.295 ns; Loc. = LCFF_X25_Y2_N1; Fanout = 2; REG Node = 'div16:inst2\|count\[3\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "2.078 ns" { clk~clkctrl div16:inst2|count[3] } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.978 ns) + CELL(0.000 ns) 4.273 ns div16:inst2\|count\[3\]~clkctrl 4 COMB CLKCTRL_G13 16 " "Info: 4: + IC(0.978 ns) + CELL(0.000 ns) = 4.273 ns; Loc. = CLKCTRL_G13; Fanout = 16; COMB Node = 'div16:inst2\|count\[3\]~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.978 ns" { div16:inst2|count[3] div16:inst2|count[3]~clkctrl } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.989 ns) 6.351 ns lcd:inst\|clkcnt\[6\] 5 REG LCFF_X25_Y3_N9 3 " "Info: 5: + IC(1.089 ns) + CELL(0.989 ns) = 6.351 ns; Loc. = LCFF_X25_Y3_N9; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[6\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "2.078 ns" { div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.378 ns) 7.159 ns lcd:inst\|reduce_nor~378 6 COMB LCCOMB_X25_Y3_N28 1 " "Info: 6: + IC(0.430 ns) + CELL(0.378 ns) = 7.159 ns; Loc. = LCCOMB_X25_Y3_N28; Fanout = 1; COMB Node = 'lcd:inst\|reduce_nor~378'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.808 ns" { lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(0.210 ns) 7.729 ns lcd:inst\|reduce_nor~380 7 COMB LCCOMB_X25_Y3_N22 7 " "Info: 7: + IC(0.360 ns) + CELL(0.210 ns) = 7.729 ns; Loc. = LCCOMB_X25_Y3_N22; Fanout = 7; COMB Node = 'lcd:inst\|reduce_nor~380'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.570 ns" { lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.989 ns) 9.058 ns lcd:inst\|clkdiv 8 REG LCFF_X25_Y3_N19 2 " "Info: 8: + IC(0.340 ns) + CELL(0.989 ns) = 9.058 ns; Loc. = LCFF_X25_Y3_N19; Fanout = 2; REG Node = 'lcd:inst\|clkdiv'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.329 ns" { lcd:inst|reduce_nor~380 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.000 ns) 10.075 ns lcd:inst\|clkdiv~clkctrl 9 COMB CLKCTRL_G15 2 " "Info: 9: + IC(1.017 ns) + CELL(0.000 ns) = 10.075 ns; Loc. = CLKCTRL_G15; Fanout = 2; COMB Node = 'lcd:inst\|clkdiv~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.017 ns" { lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.989 ns) 12.155 ns lcd:inst\|clk_int 10 REG LCFF_X25_Y1_N13 2 " "Info: 10: + IC(1.091 ns) + CELL(0.989 ns) = 12.155 ns; Loc. = LCFF_X25_Y1_N13; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "2.080 ns" { lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.000 ns) 13.341 ns lcd:inst\|clk_int~clkctrl 11 COMB CLKCTRL_G12 19 " "Info: 11: + IC(1.186 ns) + CELL(0.000 ns) = 13.341 ns; Loc. = CLKCTRL_G12; Fanout = 19; COMB Node = 'lcd:inst\|clk_int~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.186 ns" { lcd:inst|clk_int lcd:inst|clk_int~clkctrl } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.088 ns) + CELL(0.679 ns) 15.108 ns lcd:inst\|state\[4\] 12 REG LCFF_X18_Y2_N21 6 " "Info: 12: + IC(1.088 ns) + CELL(0.679 ns) = 15.108 ns; Loc. = LCFF_X18_Y2_N21; Fanout = 6; REG Node = 'lcd:inst\|state\[4\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.767 ns" { lcd:inst|clk_int~clkctrl lcd:inst|state[4] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.323 ns 41.85 % " "Info: Total cell delay = 6.323 ns ( 41.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.785 ns 58.15 % " "Info: Total interconnect delay = 8.785 ns ( 58.15 % )" {  } {  } 0}  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "15.108 ns" { clk clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|state[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.108 ns" { clk clk~combout clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|state[4] } { 0.000ns 0.000ns 0.117ns 1.089ns 0.978ns 1.089ns 0.430ns 0.360ns 0.340ns 1.017ns 1.091ns 1.186ns 1.088ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.989ns 0.378ns 0.210ns 0.989ns 0.000ns 0.989ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 16.142 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 16.142 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP2C20/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.217 ns clk~clkctrl 2 COMB CLKCTRL_G14 4 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G14; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.117 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP2C20/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.989 ns) 3.295 ns div16:inst2\|count\[3\] 3 REG LCFF_X25_Y2_N1 2 " "Info: 3: + IC(1.089 ns) + CELL(0.989 ns) = 3.295 ns; Loc. = LCFF_X25_Y2_N1; Fanout = 2; REG Node = 'div16:inst2\|count\[3\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "2.078 ns" { clk~clkctrl div16:inst2|count[3] } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.978 ns) + CELL(0.000 ns) 4.273 ns div16:inst2\|count\[3\]~clkctrl 4 COMB CLKCTRL_G13 16 " "Info: 4: + IC(0.978 ns) + CELL(0.000 ns) = 4.273 ns; Loc. = CLKCTRL_G13; Fanout = 16; COMB Node = 'div16:inst2\|count\[3\]~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "0.978 ns" { div16:inst2|count[3] div16:inst2|count[3]~clkctrl } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.989 ns) 6.351 ns lcd:inst\|clkcnt\[13\] 5 REG LCFF_X24_Y3_N27 3 " "Info: 5: + IC(1.089 ns) + CELL(0.989 ns) = 6.351 ns; Loc. = LCFF_X24_Y3_N27; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[13\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "2.078 ns" { div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.770 ns) + CELL(0.636 ns) 7.757 ns lcd:inst\|reduce_nor~376 6 COMB LCCOMB_X25_Y3_N30 1 " "Info: 6: + IC(0.770 ns) + CELL(0.636 ns) = 7.757 ns; Loc. = LCCOMB_X25_Y3_N30; Fanout = 1; COMB Node = 'lcd:inst\|reduce_nor~376'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.406 ns" { lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.636 ns) 8.763 ns lcd:inst\|reduce_nor~380 7 COMB LCCOMB_X25_Y3_N22 7 " "Info: 7: + IC(0.370 ns) + CELL(0.636 ns) = 8.763 ns; Loc. = LCCOMB_X25_Y3_N22; Fanout = 7; COMB Node = 'lcd:inst\|reduce_nor~380'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.006 ns" { lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.989 ns) 10.092 ns lcd:inst\|clkdiv 8 REG LCFF_X25_Y3_N19 2 " "Info: 8: + IC(0.340 ns) + CELL(0.989 ns) = 10.092 ns; Loc. = LCFF_X25_Y3_N19; Fanout = 2; REG Node = 'lcd:inst\|clkdiv'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.329 ns" { lcd:inst|reduce_nor~380 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.000 ns) 11.109 ns lcd:inst\|clkdiv~clkctrl 9 COMB CLKCTRL_G15 2 " "Info: 9: + IC(1.017 ns) + CELL(0.000 ns) = 11.109 ns; Loc. = CLKCTRL_G15; Fanout = 2; COMB Node = 'lcd:inst\|clkdiv~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.017 ns" { lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.989 ns) 13.189 ns lcd:inst\|clk_int 10 REG LCFF_X25_Y1_N13 2 " "Info: 10: + IC(1.091 ns) + CELL(0.989 ns) = 13.189 ns; Loc. = LCFF_X25_Y1_N13; Fanout = 2; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "2.080 ns" { lcd:inst|clkdiv~clkctrl lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.186 ns) + CELL(0.000 ns) 14.375 ns lcd:inst\|clk_int~clkctrl 11 COMB CLKCTRL_G12 19 " "Info: 11: + IC(1.186 ns) + CELL(0.000 ns) = 14.375 ns; Loc. = CLKCTRL_G12; Fanout = 19; COMB Node = 'lcd:inst\|clk_int~clkctrl'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.186 ns" { lcd:inst|clk_int lcd:inst|clk_int~clkctrl } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.088 ns) + CELL(0.679 ns) 16.142 ns lcd:inst\|state\[2\] 12 REG LCFF_X18_Y2_N7 8 " "Info: 12: + IC(1.088 ns) + CELL(0.679 ns) = 16.142 ns; Loc. = LCFF_X18_Y2_N7; Fanout = 8; REG Node = 'lcd:inst\|state\[2\]'" {  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "1.767 ns" { lcd:inst|clk_int~clkctrl lcd:inst|state[2] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.007 ns 43.41 % " "Info: Total cell delay = 7.007 ns ( 43.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.135 ns 56.59 % " "Info: Total interconnect delay = 9.135 ns ( 56.59 % )" {  } {  } 0}  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "16.142 ns" { clk clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|state[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.142 ns" { clk clk~combout clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|state[2] } { 0.000ns 0.000ns 0.117ns 1.089ns 0.978ns 1.089ns 0.770ns 0.370ns 0.340ns 1.017ns 1.091ns 1.186ns 1.088ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.989ns 0.636ns 0.636ns 0.989ns 0.000ns 0.989ns 0.000ns 0.679ns } } }  } 0}  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "15.108 ns" { clk clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|state[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.108 ns" { clk clk~combout clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|state[4] } { 0.000ns 0.000ns 0.117ns 1.089ns 0.978ns 1.089ns 0.430ns 0.360ns 0.340ns 1.017ns 1.091ns 1.186ns 1.088ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.989ns 0.378ns 0.210ns 0.989ns 0.000ns 0.989ns 0.000ns 0.679ns } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "16.142 ns" { clk clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|state[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.142 ns" { clk clk~combout clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|state[2] } { 0.000ns 0.000ns 0.117ns 1.089ns 0.978ns 1.089ns 0.770ns 0.370ns 0.340ns 1.017ns 1.091ns 1.186ns 1.088ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.989ns 0.636ns 0.636ns 0.989ns 0.000ns 0.989ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0}  } { { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "5.314 ns" { lcd:inst|state[2] lcd:inst|reduce_nor~372 lcd:inst|reduce_nor~16 lcd:inst|Select~259 lcd:inst|Select~260 lcd:inst|state[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.314 ns" { lcd:inst|state[2] lcd:inst|reduce_nor~372 lcd:inst|reduce_nor~16 lcd:inst|Select~259 lcd:inst|Select~260 lcd:inst|state[4] } { 0.000ns 0.769ns 0.382ns 0.725ns 1.042ns 0.000ns } { 0.000ns 0.378ns 0.636ns 0.636ns 0.636ns 0.110ns } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "15.108 ns" { clk clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|state[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.108 ns" { clk clk~combout clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|state[4] } { 0.000ns 0.000ns 0.117ns 1.089ns 0.978ns 1.089ns 0.430ns 0.360ns 0.340ns 1.017ns 1.091ns 1.186ns 1.088ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.989ns 0.378ns 0.210ns 0.989ns 0.000ns 0.989ns 0.000ns 0.679ns } } } { "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP2C20/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP2C20/S4_LCD_VHDL/Proj/" "" "16.142 ns" { clk clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|state[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.142 ns" { clk clk~combout clk~clkctrl div16:inst2|count[3] div16:inst2|count[3]~clkctrl lcd:inst|clkcnt[13] lcd:inst|reduce_nor~376 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clkdiv~clkctrl lcd:inst|clk_int lcd:inst|clk_int~clkctrl lcd:inst|state[2] } { 0.000ns 0.000ns 0.117ns 1.089ns 0.978ns 1.089ns 0.770ns 0.370ns 0.340ns 1.017ns 1.091ns 1.186ns 1.088ns } { 0.000ns 1.100ns 0.000ns 0.989ns 0.000ns 0.989ns 0.636ns 0.636ns 0.989ns 0.000ns 0.989ns 0.000ns 0.679ns } } }  } 0}