proj.map.rpt

采用vhdl语言编写的16x2液晶显示模块的驱动程序。在quartus中编译完成

; ../src/char_ram.vhd              ; yes             ; User VHDL File                     ; E:/code/EP2C20/S4_LCD_VHDL/src/char_ram.vhd  ;
; ../src/div16.v                   ; yes             ; User Verilog HDL File              ; E:/code/EP2C20/S4_LCD_VHDL/src/div16.v       ;
; ../src/lcd.vhd                   ; yes             ; User VHDL File                     ; E:/code/EP2C20/S4_LCD_VHDL/src/lcd.vhd       ;
; lcd_test.bdf                     ; yes             ; User Block Diagram/Schematic File  ; E:/code/EP2C20/S4_LCD_VHDL/Proj/lcd_test.bdf ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Total combinational functions               ; 153     ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 76      ;
;     -- 3 input functions                    ; 13      ;
;     -- <=2 input functions                  ; 64      ;
;         -- Combinational cells for routing  ; 0       ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 122     ;
;     -- arithmetic mode                      ; 31      ;
; Total registers                             ; 42      ;
; I/O pins                                    ; 14      ;
; Maximum fan-out node                        ; SYS_RST ;
; Maximum fan-out                             ; 42      ;
; Total fan-out                               ; 626     ;
; Average fan-out                             ; 3.00    ;
+---------------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                     ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name            ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+
; |lcd_test                  ; 153 (0)           ; 42 (0)       ; 0           ; 0            ; 0       ; 0         ; 14   ; 0            ; |lcd_test                      ;
;    |div16:inst2|           ; 6 (6)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lcd_test|div16:inst2          ;
;    |lcd:inst|              ; 147 (139)         ; 38 (38)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lcd_test|lcd:inst             ;
;       |char_ram:aa|        ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |lcd_test|lcd:inst|char_ram:aa ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 42    ;
; Number of registers using Synchronous Clear  ; 7     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 42    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 15    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |lcd_test|lcd:inst|div_counter[0] ;
; 6:1                ; 7 bits    ; 28 LEs        ; 7 LEs                ; 21 LEs                 ; Yes        ; |lcd_test|lcd:inst|counter[0]     ;
; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |lcd_test|lcd:inst|char_addr[0]   ;
; 8:1                ; 7 bits    ; 35 LEs        ; 35 LEs               ; 0 LEs                  ; No         ; |lcd_test|lcd:inst|data~69        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/code/EP2C20/S4_LCD_VHDL/Proj/Proj.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Tue Dec 05 14:53:27 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LCD_Test -c Proj
Info: Found 2 design units, including 1 entities, in source file ../src/char_ram.vhd
    Info: Found design unit 1: char_ram-fun
    Info: Found entity 1: char_ram
Info: Found 1 design units, including 1 entities, in source file ../src/div16.v
    Info: Found entity 1: div16
Info: Found 2 design units, including 1 entities, in source file ../src/lcd.vhd
    Info: Found design unit 1: lcd-Behavioral
    Info: Found entity 1: lcd
Info: Found 1 design units, including 1 entities, in source file lcd_test.bdf
    Info: Found entity 1: lcd_test
Info: Elaborating entity "lcd_test" for the top level hierarchy
Warning: Port "lcd_e" of type lcd and instance "inst" is missing source signal
Info: Elaborating entity "lcd" for hierarchy "lcd:inst"
Info: Elaborating entity "char_ram" for hierarchy "lcd:inst|char_ram:aa"
Info: Elaborating entity "div16" for hierarchy "div16:inst2"
Warning: Verilog HDL assignment warning at div16.v(10): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at div16.v(12): truncated value with size 32 to match size of target (4)
Warning: Reduced register "lcd:inst|state[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "lcd:inst|state[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "lcd:inst|state[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "lcd:inst|state[1]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "LCD_DIR" stuck at VCC
Info: Implemented 209 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 12 output pins
    Info: Implemented 195 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Processing ended: Tue Dec 05 14:53:31 2006
    Info: Elapsed time: 00:00:05