de2_default.map.qmsg

DE2开发版的默认程序

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(152) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(152): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 152 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 VGA_Controller.v(153) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(153): truncated value with size 32 to match size of target (1)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 153 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(159) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(159): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 159 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(161) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(161): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 161 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 VGA_Controller.v(164) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(164): truncated value with size 32 to match size of target (1)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 164 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 VGA_Controller.v(166) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(166): truncated value with size 32 to match size of target (1)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 166 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(175) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(175): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 175 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 VGA_Controller.v(176) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(176): truncated value with size 32 to match size of target (1)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 176 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(185) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(185): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 185 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(187) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(187): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 187 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 VGA_Controller.v(190) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(190): truncated value with size 32 to match size of target (1)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 190 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 VGA_Controller.v(192) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(192): truncated value with size 32 to match size of target (1)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 192 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA_OSD_RAM VGA_OSD_RAM:u2 " "Info: Elaborating entity \"VGA_OSD_RAM\" for hierarchy \"VGA_OSD_RAM:u2\"" {  } { { "DE2_Default.v" "u2" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 382 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_OSD_RAM.v(50) " "Warning: Verilog HDL assignment warning at VGA_OSD_RAM.v(50): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_OSD_RAM.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_OSD_RAM.v" 50 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_OSD_RAM.v(51) " "Warning: Verilog HDL assignment warning at VGA_OSD_RAM.v(51): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_OSD_RAM.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_OSD_RAM.v" 51 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_OSD_RAM.v(52) " "Warning: Verilog HDL assignment warning at VGA_OSD_RAM.v(52): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_OSD_RAM.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_OSD_RAM.v" 52 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 VGA_OSD_RAM.v(53) " "Warning: Verilog HDL assignment warning at VGA_OSD_RAM.v(53): truncated value with size 32 to match size of target (3)" {  } { { "VGA_Controller/VGA_OSD_RAM.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_OSD_RAM.v" 53 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 VGA_OSD_RAM.v(54) " "Warning: Verilog HDL assignment warning at VGA_OSD_RAM.v(54): truncated value with size 32 to match size of target (3)" {  } { { "VGA_Controller/VGA_OSD_RAM.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_OSD_RAM.v" 54 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Img_RAM VGA_OSD_RAM:u2\|Img_RAM:u0 " "Info: Elaborating entity \"Img_RAM\" for hierarchy \"VGA_OSD_RAM:u2\|Img_RAM:u0\"" {  } { { "VGA_Controller/VGA_OSD_RAM.v" "u0" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_OSD_RAM.v" 74 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\"" {  } { { "VGA_Controller/Img_RAM.v" "altsyncram_component" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/Img_RAM.v" 79 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_e3f1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_e3f1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_e3f1 " "Info: Found entity 1: altsyncram_e3f1" {  } { { "db/altsyncram_e3f1.tdf" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/altsyncram_e3f1.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_e3f1 VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated " "Info: Elaborating entity \"altsyncram_e3f1\" for hierarchy \"VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_8en1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_8en1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_8en1 " "Info: Found entity 1: altsyncram_8en1" {  } { { "db/altsyncram_8en1.tdf" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/altsyncram_8en1.tdf" 40 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_8en1 VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1 " "Info: Elaborating entity \"altsyncram_8en1\" for hierarchy \"VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\"" {  } { { "db/altsyncram_e3f1.tdf" "altsyncram1" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/altsyncram_e3f1.tdf" 35 2 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_1qa.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_1qa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_1qa " "Info: Found entity 1: decode_1qa" {  } { { "db/decode_1qa.tdf" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/decode_1qa.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_1qa VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|decode_1qa:decode3 " "Info: Elaborating entity \"decode_1qa\" for hierarchy \"VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|decode_1qa:decode3\"" {  } { { "db/altsyncram_8en1.tdf" "decode3" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/altsyncram_8en1.tdf" 56 2 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_hkb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_hkb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_hkb " "Info: Found entity 1: mux_hkb" {  } { { "db/mux_hkb.tdf" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/mux_hkb.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_hkb VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|mux_hkb:mux5 " "Info: Elaborating entity \"mux_hkb\" for hierarchy \"VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|mux_hkb:mux5\"" {  } { { "db/altsyncram_8en1.tdf" "mux5" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/altsyncram_8en1.tdf" 60 2 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_akb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_akb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_akb " "Info: Found entity 1: mux_akb" {  } { { "db/mux_akb.tdf" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/mux_akb.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_akb VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|mux_akb:mux6 " "Info: Elaborating entity \"mux_akb\" for hierarchy \"VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|mux_akb:mux6\"" {  } { { "db/altsyncram_8en1.tdf" "mux6" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/altsyncram_8en1.tdf" 61 2 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_AV_Config I2C_AV_Config:u3 " "Info: Elaborating entity \"I2C_AV_Config\" for hierarchy \"I2C_AV_Config:u3\"" {  } { { "DE2_Default.v" "u3" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 389 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_AV_Config.v(48) " "Warning: Verilog HDL assignment warning at I2C_AV_Config.v(48): truncated value with size 32 to match size of target (1)" {  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 I2C_AV_Config.v(49) " "Warning: Verilog HDL assignment warning at I2C_AV_Config.v(49): truncated value with size 32 to match size of target (16)" {  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 I2C_AV_Config.v(54) " "Warning: Verilog HDL assignment warning at I2C_AV_Config.v(54): truncated value with size 32 to match size of target (16)" {  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 54 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 I2C_AV_Config.v(57) " "Warning: Verilog HDL assignment warning at I2C_AV_Config.v(57): truncated value with size 32 to match size of target (16)" {  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 57 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 I2C_AV_Config.v(77) " "Warning: Verilog HDL assignment warning at I2C_AV_Config.v(77): truncated value with size 32 to match size of target (6)" {  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 77 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_AV_Config.v(79) " "Warning: Verilog HDL assignment warning at I2C_AV_Config.v(79): truncated value with size 32 to match size of target (1)" {  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 79 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_AV_Config.v(91) " "Warning: Verilog HDL assignment warning at I2C_AV_Config.v(91): truncated value with size 32 to match size of target (1)" {  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 91 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_AV_Config.v(101) " "Warning: Verilog HDL assignment warning at I2C_AV_Config.v(101): truncated value with size 32 to match size of target (1)" {  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 101 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 I2C_AV_Config.v(105) " "Warning: Verilog HDL assignment warning at I2C_AV_Config.v(105): truncated value with size 32 to match size of target (6)" {  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 105 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 6 I2C_AV_Config.v(118) " "Warning: (10271) Verilog HDL Case Statement warning at I2C_AV_Config.v(118): size of case item expression (32) exceeds the size of the case expression (6)" {  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 6 I2C_AV_Config.v(119) " "Warning: (10271) Verilog HDL Case Statement warning at I2C_AV_Config.v(119): size of case item expression (32) exceeds the size of the case expression (6)" {  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 119 0 0 } }  } 0}