⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 de2_default.map.qmsg

📁 DE2开发版的默认程序
💻 QMSG
📖 第 1 页 / 共 5 页
字号:
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAM_UB_N DE2_Default.v(226) " "Warning: Output port \"SRAM_UB_N\" at DE2_Default.v(226) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 226 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAM_LB_N DE2_Default.v(227) " "Warning: Output port \"SRAM_LB_N\" at DE2_Default.v(227) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 227 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAM_WE_N DE2_Default.v(228) " "Warning: Output port \"SRAM_WE_N\" at DE2_Default.v(228) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 228 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAM_CE_N DE2_Default.v(229) " "Warning: Output port \"SRAM_CE_N\" at DE2_Default.v(229) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 229 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAM_OE_N DE2_Default.v(230) " "Warning: Output port \"SRAM_OE_N\" at DE2_Default.v(230) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 230 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "OTG_ADDR\[1\] DE2_Default.v(233) " "Warning: Output port \"OTG_ADDR\[1\]\" at DE2_Default.v(233) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 233 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "OTG_ADDR\[0\] DE2_Default.v(233) " "Warning: Output port \"OTG_ADDR\[0\]\" at DE2_Default.v(233) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 233 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "OTG_CS_N DE2_Default.v(234) " "Warning: Output port \"OTG_CS_N\" at DE2_Default.v(234) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 234 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "OTG_RD_N DE2_Default.v(235) " "Warning: Output port \"OTG_RD_N\" at DE2_Default.v(235) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 235 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "OTG_WR_N DE2_Default.v(236) " "Warning: Output port \"OTG_WR_N\" at DE2_Default.v(236) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 236 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "OTG_RST_N DE2_Default.v(237) " "Warning: Output port \"OTG_RST_N\" at DE2_Default.v(237) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 237 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "OTG_FSPEED DE2_Default.v(238) " "Warning: Output port \"OTG_FSPEED\" at DE2_Default.v(238) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 238 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "OTG_LSPEED DE2_Default.v(239) " "Warning: Output port \"OTG_LSPEED\" at DE2_Default.v(239) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 239 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "OTG_DACK0_N DE2_Default.v(244) " "Warning: Output port \"OTG_DACK0_N\" at DE2_Default.v(244) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 244 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "OTG_DACK1_N DE2_Default.v(245) " "Warning: Output port \"OTG_DACK1_N\" at DE2_Default.v(245) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 245 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SD_CLK DE2_Default.v(257) " "Warning: Output port \"SD_CLK\" at DE2_Default.v(257) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 257 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "TDO DE2_Default.v(268) " "Warning: Output port \"TDO\" at DE2_Default.v(268) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 268 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "ENET_CMD DE2_Default.v(280) " "Warning: Output port \"ENET_CMD\" at DE2_Default.v(280) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 280 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "ENET_CS_N DE2_Default.v(281) " "Warning: Output port \"ENET_CS_N\" at DE2_Default.v(281) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 281 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "ENET_WR_N DE2_Default.v(282) " "Warning: Output port \"ENET_WR_N\" at DE2_Default.v(282) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 282 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "ENET_RD_N DE2_Default.v(283) " "Warning: Output port \"ENET_RD_N\" at DE2_Default.v(283) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 283 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "ENET_RST_N DE2_Default.v(284) " "Warning: Output port \"ENET_RST_N\" at DE2_Default.v(284) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 284 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "ENET_CLK DE2_Default.v(286) " "Warning: Output port \"ENET_CLK\" at DE2_Default.v(286) has no driver" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 286 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay Reset_Delay:r0 " "Info: Elaborating entity \"Reset_Delay\" for hierarchy \"Reset_Delay:r0\"" {  } { { "DE2_Default.v" "r0" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 344 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 Reset_Delay.v(10) " "Warning: Verilog HDL assignment warning at Reset_Delay.v(10): truncated value with size 32 to match size of target (20)" {  } { { "Reset_Delay.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/Reset_Delay.v" 10 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA_Audio_PLL VGA_Audio_PLL:p1 " "Info: Elaborating entity \"VGA_Audio_PLL\" for hierarchy \"VGA_Audio_PLL:p1\"" {  } { { "DE2_Default.v" "p1" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 346 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll VGA_Audio_PLL:p1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"VGA_Audio_PLL:p1\|altpll:altpll_component\"" {  } { { "VGA_Audio_PLL.v" "altpll_component" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Audio_PLL.v" 89 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT_8 SEG7_LUT_8:u0 " "Info: Elaborating entity \"SEG7_LUT_8\" for hierarchy \"SEG7_LUT_8:u0\"" {  } { { "DE2_Default.v" "u0" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 348 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT SEG7_LUT_8:u0\|SEG7_LUT:u0 " "Info: Elaborating entity \"SEG7_LUT\" for hierarchy \"SEG7_LUT_8:u0\|SEG7_LUT:u0\"" {  } { { "SEG7_LUT_8.v" "u0" { Text "E:/zhangwei/fpga_pro/DE2_Default/SEG7_LUT_8.v" 5 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA_Controller VGA_Controller:u1 " "Info: Elaborating entity \"VGA_Controller\" for hierarchy \"VGA_Controller:u1\"" {  } { { "DE2_Default.v" "u1" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 366 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(74) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(74): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 74 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(77) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(77): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 77 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(80) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(80): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 80 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(89) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(89): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 89 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(90) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(90): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 90 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 VGA_Controller.v(91) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(91): truncated value with size 32 to match size of target (20)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 91 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(98) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(98): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 98 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(99) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(99): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 99 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 VGA_Controller.v(100) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(100): truncated value with size 32 to match size of target (20)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 100 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(110) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(110): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 110 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(111) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(111): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 111 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(112) " "Warning: Verilog HDL assignment warning at VGA_Controller.v(112): truncated value with size 32 to match size of target (10)" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 112 0 0 } }  } 0}

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -